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📄 mux_mcb.tdf

📁 采用DDS技术的波形发生器(FPGA实现)
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone" LPM_SIZE=4 LPM_WIDTH=39 LPM_WIDTHS=2 data result sel
--VERSION_BEGIN 6.0 cbx_lpm_mux 2006:01:09:11:16:16:SJ cbx_mgl 2006:04:14:11:14:36:SJ  VERSION_END


--  Copyright (C) 1991-2006 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 78 
SUBDESIGN mux_mcb
( 
	data[155..0]	:	input;
	result[38..0]	:	output;
	sel[1..0]	:	input;
) 
VARIABLE 
	result_node[38..0]	: WIRE;
	sel_node[1..0]	: WIRE;
	w_data1351w[3..0]	: WIRE;
	w_data1381w[3..0]	: WIRE;
	w_data1406w[3..0]	: WIRE;
	w_data1431w[3..0]	: WIRE;
	w_data1456w[3..0]	: WIRE;
	w_data1481w[3..0]	: WIRE;
	w_data1506w[3..0]	: WIRE;
	w_data1531w[3..0]	: WIRE;
	w_data1556w[3..0]	: WIRE;
	w_data1581w[3..0]	: WIRE;
	w_data1606w[3..0]	: WIRE;
	w_data1631w[3..0]	: WIRE;
	w_data1656w[3..0]	: WIRE;
	w_data1681w[3..0]	: WIRE;
	w_data1706w[3..0]	: WIRE;
	w_data1731w[3..0]	: WIRE;
	w_data1756w[3..0]	: WIRE;
	w_data1781w[3..0]	: WIRE;
	w_data1806w[3..0]	: WIRE;
	w_data1831w[3..0]	: WIRE;
	w_data1856w[3..0]	: WIRE;
	w_data1881w[3..0]	: WIRE;
	w_data1906w[3..0]	: WIRE;
	w_data1931w[3..0]	: WIRE;
	w_data1956w[3..0]	: WIRE;
	w_data1981w[3..0]	: WIRE;
	w_data2006w[3..0]	: WIRE;
	w_data2031w[3..0]	: WIRE;
	w_data2056w[3..0]	: WIRE;
	w_data2081w[3..0]	: WIRE;
	w_data2106w[3..0]	: WIRE;
	w_data2131w[3..0]	: WIRE;
	w_data2156w[3..0]	: WIRE;
	w_data2181w[3..0]	: WIRE;
	w_data2206w[3..0]	: WIRE;
	w_data2231w[3..0]	: WIRE;
	w_data2256w[3..0]	: WIRE;
	w_data2281w[3..0]	: WIRE;
	w_data2306w[3..0]	: WIRE;
	w_result1363w	: WIRE;
	w_result1393w	: WIRE;
	w_result1418w	: WIRE;
	w_result1443w	: WIRE;
	w_result1468w	: WIRE;
	w_result1493w	: WIRE;
	w_result1518w	: WIRE;
	w_result1543w	: WIRE;
	w_result1568w	: WIRE;
	w_result1593w	: WIRE;
	w_result1618w	: WIRE;
	w_result1643w	: WIRE;
	w_result1668w	: WIRE;
	w_result1693w	: WIRE;
	w_result1718w	: WIRE;
	w_result1743w	: WIRE;
	w_result1768w	: WIRE;
	w_result1793w	: WIRE;
	w_result1818w	: WIRE;
	w_result1843w	: WIRE;
	w_result1868w	: WIRE;
	w_result1893w	: WIRE;
	w_result1918w	: WIRE;
	w_result1943w	: WIRE;
	w_result1968w	: WIRE;
	w_result1993w	: WIRE;
	w_result2018w	: WIRE;
	w_result2043w	: WIRE;

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