dds.map.qmsg

采用DDS技术的波形发生器(FPGA实现)

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_fcw add_fcw:inst " "Info: Elaborating entity \"add_fcw\" for hierarchy \"add_fcw:inst\"" {  } { { "dds.bdf" "inst" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 dds_good/dds.bdf" { { 272 208 352 368 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fangbo fangbo:inst10 " "Info: Elaborating entity \"fangbo\" for hierarchy \"fangbo:inst10\"" {  } { { "dds.bdf" "inst10" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 dds_good/dds.bdf" { { 632 600 736 728 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "juchi_address juchi_address:inst8 " "Info: Elaborating entity \"juchi_address\" for hierarchy \"juchi_address:inst8\"" {  } { { "dds.bdf" "inst8" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 dds_good/dds.bdf" { { 520 488 656 616 "inst8" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin_out sin_out:inst4 " "Info: Elaborating entity \"sin_out\" for hierarchy \"sin_out:inst4\"" {  } { { "dds.bdf" "inst4" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 dds_good/dds.bdf" { { 280 920 1104 376 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sin_add sin_add:inst2 " "Info: Elaborating entity \"sin_add\" for hierarchy \"sin_add:inst2\"" {  } { { "dds.bdf" "inst2" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 dds_good/dds.bdf" { { 280 480 664 376 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "sinrom.vhd 2 1 " "Warning: Using design file sinrom.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sinrom-SYN " "Info: Found design unit 1: sinrom-SYN" {  } { { "sinrom.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 dds_good/sinrom.vhd" 49 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sinrom " "Info: Found entity 1: sinrom" {  } { { "sinrom.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 dds_good/sinrom.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sinrom sinrom:inst3 " "Info: Elaborating entity \"sinrom\" for hierarchy \"sinrom:inst3\"" {  } { { "dds.bdf" "inst3" { Schematic "C:/Documents and Settings/Administrator/桌面/复件 dds_good/dds.bdf" { { 280 712 864 376 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram sinrom:inst3\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"sinrom:inst3\|altsyncram:altsyncram_component\"" {  } { { "sinrom.vhd" "altsyncram_component" { Text "C:/Documents and Settings/Administrator/桌面/复件 dds_good/sinrom.vhd" 80 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sinrom:inst3\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"sinrom:inst3\|altsyncram:altsyncram_component\"" {  } { { "sinrom.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 dds_good/sinrom.vhd" 80 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hk31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hk31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hk31 " "Info: Found entity 1: altsyncram_hk31" {  } { { "db/altsyncram_hk31.tdf" "" { Text "C:/Documents and Settings/Administrator/桌面/复件 dds_good/db/altsyncram_hk31.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_hk31 sinrom:inst3\|altsyncram:altsyncram_component\|altsyncram_hk31:auto_generated " "Info: Elaborating entity \"altsyncram_hk31\" for hierarchy \"sinrom:inst3\|altsyncram:altsyncram_component\|altsyncram_hk31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "f:/altera/libraries/megafunctions/altsyncram.tdf" 905 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/libraries/megafunctions/sld_signaltap.vhd 3 1 " "Info: Found 3 design units, including 1 entities, in source file f:/altera/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "f:/altera/libraries/megafunctions/sld_signaltap.vhd" "" { Text "f:/altera/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap-rtl " "Info: Found design unit 2: sld_signaltap-rtl" {  } { { "f:/altera/libraries/megafunctions/sld_signaltap.vhd" "" { Text "f:/altera/libraries/megafunctions/sld_signaltap.vhd" 175 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "f:/altera/libraries/megafunctions/sld_signaltap.vhd" "" { Text "f:/altera/libraries/megafunctions/sld_signaltap.vhd" 85 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "sld_signaltap:auto_signaltap_0 " "Info: Elaborated megafunction instantiation \"sld_signaltap:auto_signaltap_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}