stp1.stp

采用DDS技术的波形发生器(FPGA实现)

<session jtag_chain="ByteBlasterII [LPT1]" jtag_device="@1: EP1C3 (0x020810DD)" sof_file="">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <instance compilation_mode="full" entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="4"/>
    <position_info>
      <single attribute="active tab" value="0"/>
      <single attribute="data horizontal scroll position" value="400"/>
      <single attribute="data vertical scroll position" value="1"/>
      <single attribute="setup horizontal scroll position" value="0"/>
      <single attribute="setup vertical scroll position" value="2"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom level numerator" value="1"/>
      <single attribute="zoom offset denominator" value="1"/>
      <single attribute="zoom offset numerator" value="130944"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2007/08/06 16:51:50  #0">
      <clock name="add_fcw:inst|clk" polarity="posedge"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire connection_status="true" name="a-b" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="clear" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="cs" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="en" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fcw[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="mcu_add[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="mcu_add[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="output[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="selectwave:inst11|sel[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="selectwave:inst11|sel[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[7]" tap_mode="classic" type="combinatorial"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire connection_status="true" name="a-b" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="clear" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="cs" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="en" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="fcw[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="fcw[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="mcu_add[0]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="mcu_add[1]" tap_mode="classic" type="input pin"/>
          <wire connection_status="true" name="output[0]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[1]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[2]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[3]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[4]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[5]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[6]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="output[7]" tap_mode="classic" type="output pin"/>
          <wire connection_status="true" name="selectwave:inst11|sel[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="selectwave:inst11|sel[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sin_add:inst2|add_out[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="sinrom:inst3|address[7]" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <setup_view>
          <net is_signal_inverted="no" name="a-b"/>
          <net is_signal_inverted="no" name="clear"/>
          <net is_signal_inverted="no" name="cs"/>
          <net is_signal_inverted="no" name="en"/>
          <bus is_signal_inverted="no" link="all" name="fcw" order="msb_to_lsb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="fcw[7]"/>
            <net is_signal_inverted="no" name="fcw[6]"/>
            <net is_signal_inverted="no" name="fcw[5]"/>
            <net is_signal_inverted="no" name="fcw[4]"/>
            <net is_signal_inverted="no" name="fcw[3]"/>