dds.tan.rpt

采用DDS技术的波形发生器(FPGA实现)

; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                          ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name              ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; gclock                       ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; altera_internal_jtag~TCKUTAP ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+------------------------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'gclock'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                                                                                                             ; To                                                                                                                                                   ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 133.03 MHz ( period = 7.517 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_seg_state_machine:sm2|status_out[0]                                               ; gclock     ; gclock   ; None                        ; None                      ; 7.271 ns                ;
; N/A                                     ; 133.03 MHz ( period = 7.517 ns )                    ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1|regoutff ; sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_state_machine:sm1|post_trigger_count_enable                                       ; gclock     ; gclock   ; None                        ; None                      ; 7.271 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_datain_reg0        ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg0       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg1       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg2       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg3       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg4       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg5       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg6       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;
; N/A                                     ; 133.07 MHz ( period = 7.515 ns )                    ; sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_fgh:auto_generated|safe_q[1]                                                                                ; sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_7mi2:auto_generated|ram_block1a13~porta_address_reg7       ; gclock     ; gclock   ; None                        ; None                      ; 7.262 ns                ;