📄 tlg1100api.c
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TLG_WriteReg(base_addr, REG_0086, assert1_end);
TLG_WriteReg(base_addr, REG_0087, assert2_start);
TLG_WriteReg(base_addr, REG_0088, assert2_end);
TLG_WriteReg(base_addr, REG_0089, assert3_start);
TLG_WriteReg(base_addr, REG_008A, assert3_end);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_GetHDecimate
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetHDecimate(uint32 base_addr, uint16 *decimate) {
uint16 vidConfig4;
TLG_NULLPTR_CHECK(decimate);
TLG_ReadReg(base_addr, REG_0071, &vidConfig4);
TLGHAL_GET(*decimate, vidConfig4, REG_0071_BIT9_8_SHIFT,
REG_0071_BIT9_8_MASK);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetHDecimate
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetHDecimate(uint32 base_addr, uint16 decimate) {
uint16 vidConfig4;
TLG_BOUNDS_CHECK(decimate, TLG_ON);
TLG_ReadReg(base_addr, REG_0071, &vidConfig4);
TLGHAL_SET(vidConfig4, decimate, REG_0071_BIT9_8_SHIFT,
REG_0071_BIT9_8_MASK);
TLG_WriteReg(base_addr, REG_0071, vidConfig4);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_GetVidOutType
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetVidOutType(uint32 base_addr, uint16 *vidOutType) {
uint16 vidConfig3;
TLG_NULLPTR_CHECK(vidOutType);
TLG_ReadReg(base_addr, REG_0070, &vidConfig3);
TLGHAL_GET(*vidOutType, vidConfig3, REG_0070_BIT6_5_SHIFT,
REG_0070_BIT6_5_MASK);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetVidOutType
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetVidOutType(uint32 base_addr, uint16 vidOutType) {
uint16 vidConfig3;
TLG_BOUNDS_CHECK(vidOutType, TLG_VID_DENC);
TLG_ReadReg(base_addr, REG_0070, &vidConfig3);
TLGHAL_SET(vidConfig3, vidOutType, REG_0070_BIT6_5_SHIFT,
REG_0070_BIT6_5_MASK);
TLG_WriteReg(base_addr, REG_0070, vidConfig3);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetVGA_601_NTSC
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetVGA_601_NTSC(uint32 base_addr)
{
TLG_SetExtHSync(base_addr, 179, 818, 1, 21, 262, 284);
TLG_SetExtVSync(base_addr, 1, 21, 262, 284, 284, 284);
TLG_SetVidOutType(base_addr, TLG_VID_DENC);
TLG_Set601VideoOutClock(base_addr, TLG_INVERT);
TLG_SetHDecimate(base_addr, TLG_OFF);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetVGA_601_PAL
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetVGA_601_PAL(uint32 base_addr)
{
TLG_SetExtHSync(base_addr, 185, 824, 1, 46, 287, 359);
TLG_SetExtVSync(base_addr, 1, 46, 287, 359, 600, 625);
TLG_SetVidOutType(base_addr, TLG_VID_DENC);
TLG_Set601VideoOutClock(base_addr, TLG_INVERT);
TLG_SetHDecimate(base_addr, TLG_OFF);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_Set240x240_LCD_NTSC
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_Set240x240_LCD_NTSC(uint32 base_addr)
{
TLG_SetExtHSync(base_addr, 259, 738, 1, 21, 262, 525);
TLG_SetExtVSync(base_addr, 1, 21, 0, 0, 0, 0);
TLG_SetHDecimate(base_addr, TLG_ON);
TLG_Set601VideoOutClock(base_addr, TLG_NORMAL);
TLG_SetVidOutType(base_addr, TLG_VID_LCD);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_Set240x240_LCD_PAL
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_Set240x240_LCD_PAL(uint32 base_addr)
{
TLG_SetExtHSync(base_addr, 265, 744, 1, 46, 287, 625);
TLG_SetExtVSync(base_addr, 1, 46, 0, 0, 0, 0);
TLG_SetHDecimate(base_addr, TLG_ON);
TLG_Set601VideoOutClock(base_addr, TLG_NORMAL);
TLG_SetVidOutType(base_addr, TLG_VID_LCD);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetQVGA_NTSC
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetQVGA_NTSC(uint32 base_addr)
{
TLG_SetExtHSync(base_addr, 179, 818, 1, 21, 262, 525);
TLG_SetExtVSync(base_addr, 1, 21, 0, 0, 0, 0);
TLG_SetHDecimate(base_addr, TLG_ON);
TLG_Set601VideoOutClock(base_addr, TLG_NORMAL);
TLG_SetVidOutType(base_addr, TLG_VID_DENC);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetQVGA_PAL
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetQVGA_PAL(uint32 base_addr)
{
TLG_SetExtHSync(base_addr, 185, 824, 1, 46, 287, 625);
TLG_SetExtVSync(base_addr, 1, 46, 0, 0, 0, 0);
TLG_SetHDecimate(base_addr, TLG_ON);
TLG_Set601VideoOutClock(base_addr, TLG_NORMAL);
TLG_SetVidOutType(base_addr, TLG_VID_DENC);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_GetHSyncPolarity
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetHSyncPolarity(uint32 base_addr, uint16 *polarity) {
uint16 syncCfg;
TLG_NULLPTR_CHECK(polarity);
TLG_ReadReg(base_addr, REG_0078, &syncCfg);
TLGHAL_GET(*polarity, syncCfg, REG_0078_BIT0_SHIFT,
REG_0078_BIT0_MASK);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetHSyncPolarity
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetHSyncPolarity(uint32 base_addr, uint16 polarity) {
uint16 syncCfg;
TLG_BOUNDS_CHECK(polarity, TLG_ON);
TLG_ReadReg(base_addr, REG_0078, &syncCfg);
TLGHAL_SET(syncCfg, polarity, REG_0078_BIT0_SHIFT,
REG_0078_BIT0_MASK);
TLG_WriteReg(base_addr, REG_0078, syncCfg);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_GetVSyncPolarity
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetVSyncPolarity(uint32 base_addr, uint16 *polarity) {
uint16 syncCfg;
TLG_NULLPTR_CHECK(polarity);
TLG_ReadReg(base_addr, REG_0078, &syncCfg);
TLGHAL_GET(*polarity, syncCfg, REG_0078_BIT1_SHIFT,
REG_0078_BIT1_MASK);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetVSyncPolarity
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetVSyncPolarity(uint32 base_addr, uint16 polarity) {
uint16 syncCfg;
TLG_BOUNDS_CHECK(polarity, TLG_ON);
TLG_ReadReg(base_addr, REG_0078, &syncCfg);
TLGHAL_SET(syncCfg, polarity, REG_0078_BIT1_SHIFT,
REG_0078_BIT1_MASK);
TLG_WriteReg(base_addr, REG_0078, syncCfg);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_GetGPIOEnable
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetGPIOEnable(uint32 base_addr, uint16 *value) {
uint16 gpioEnable;
TLG_NULLPTR_CHECK(value);
TLG_ReadReg(base_addr, REG_009E, &gpioEnable);
TLGHAL_GET(*value, gpioEnable, REG_009E_BIT3_1_SHIFT,
REG_009E_BIT3_1_MASK);
return (TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetGPIOEnable
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetGPIOEnable(uint32 base_addr, uint16 mask, uint16 value) {
uint16 gpioEnable;
uint16 gpios;
TLG_BOUNDS_CHECK(mask, TLG_GPIO1|TLG_GPIO2|TLG_GPIO3);
TLG_BOUNDS_CHECK(value, TLG_GPIO1|TLG_GPIO2|TLG_GPIO3);
TLG_ReadReg(base_addr, REG_009E, &gpioEnable);
TLGHAL_GET(gpios, gpioEnable, REG_009E_BIT3_1_SHIFT,
REG_009E_BIT3_1_MASK);
value = (value & mask) | (gpios & ~mask);
TLGHAL_SET(gpioEnable, value, REG_009E_BIT3_1_SHIFT,
REG_009E_BIT3_1_MASK);
TLG_WriteReg(base_addr, REG_009E, gpioEnable);
return(TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_GetGPIOOutput
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetGPIOOutput(uint32 base_addr, uint16 *value) {
uint16 gpioOutput;
TLG_NULLPTR_CHECK(value);
TLG_ReadReg(base_addr, REG_009D, &gpioOutput);
TLGHAL_GET(*value, gpioOutput, REG_009D_BIT3_1_SHIFT,
REG_009D_BIT3_1_MASK);
return (TLG_ERR_SUCCESS);
}
/*****************************************************************************
* TLG_SetGPIOOutput
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetGPIOOutput(uint32 base_addr, uint16 mask, uint16 value) {
uint16 gpioOutput;
uint16 gpios;
TLG_BOUNDS_CHECK(mask, TLG_GPIO1|TLG_GPIO2|TLG_GPIO3);
TLG_BOUNDS_CHECK(value, TLG_GPIO1|TLG_GPIO2|TLG_GPIO3);
TLG_ReadReg(base_addr, REG_009D, &gpioOutput);
TLGHAL_GET(gpios, gpioOutput, REG_009D_BIT3_1_SHIFT,
REG_009D_BIT3_1_MASK);
value = (value & mask) | (gpios & ~mask);
TLGHAL_SET(gpioOutput, value, REG_009D_BIT3_1_SHIFT,
REG_009D_BIT3_1_MASK);
TLG_WriteReg(base_addr, REG_009D, gpioOutput);
return(TLG_ERR_SUCCESS);
}
/* 26.367 32.143 44.118 48.214 52.734 */
const uint8 tlg_aud_cic_rate[] = { 0, 210, 153, 140, 128};
const uint8 tlg_aud_deci2_sel[] = { 0, 0, 1, 1, 1};
const uint8 tlg_aud_mlen[] = { 8, 7, 6, 5, 4};
const uint8 tlg_aud_slen[] = { 0, 60, 51, 56, 0};
/*****************************************************************************
* TLG_GetAudioSampleRate
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetAudioSampleRate(uint32 base_addr, uint16 *rate) {
uint16 cic_rate, deci2_sel, mlen, slen, reg;
int i;
TLG_NULLPTR_CHECK(rate);
*rate = TLG_AUD_RATE_NONE;
TLG_ReadReg(base_addr, REG_008E, ®);
TLGHAL_GET(cic_rate, reg,
REG_008E_BIT7_0_SHIFT,
REG_008E_BIT7_0_MASK);
TLG_ReadReg(base_addr, REG_008F, ®);
TLGHAL_GET(deci2_sel, reg,
REG_008F_BIT0_SHIFT,
REG_008F_BIT0_MASK);
TLG_ReadReg(base_addr, REG_0096, ®);
TLGHAL_GET(mlen, reg, REG_0096_BIT12_8_SHIFT, REG_0096_BIT12_8_MASK);
TLGHAL_GET(slen, reg, REG_0096_BIT5_0_SHIFT, REG_0096_BIT5_0_MASK);
for (i = 0; i < TLG_AUD_RATE_52_734KHZ; i++) {
if (cic_rate == tlg_aud_cic_rate[i] &&
deci2_sel == tlg_aud_deci2_sel[i] &&
mlen == tlg_aud_mlen[i] &&
slen == tlg_aud_slen[i])
{
*rate = i + 1;
break;
}
}
return TLG_ERR_SUCCESS;
}
/*****************************************************************************
* TLG_SetAudioSampleRate
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetAudioSampleRate(uint32 base_addr, uint16 rate) {
uint16 reg;
TLG_BOUNDS_CHECK(rate, TLG_AUD_RATE_52_734KHZ);
if (rate != TLG_AUD_RATE_NONE) {
TLG_ReadReg(base_addr, REG_008E, ®);
TLGHAL_SET(reg, tlg_aud_cic_rate[rate-1],
REG_008E_BIT7_0_SHIFT,
REG_008E_BIT7_0_MASK);
TLG_WriteReg(base_addr, REG_008E, reg);
TLG_ReadReg(base_addr, REG_008F, ®);
TLGHAL_SET(reg, tlg_aud_deci2_sel[rate-1],
REG_008F_BIT0_SHIFT,
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