tlg1100api.c

泰景的模拟电视全部驱动及MTK平台界面代码

            TLG_Delay((uint16)ms);
    } while (state[0] != TLG_STATE_FINAL);
    return(TLG_ERR_SUCCESS);
#endif /* TLG_EMBEDDED_TIMERS */
}

/*****************************************************************************
* TLG_InitASYNC
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_InitASYNC(uint32 base_addr, tlg_statep state, int *ms) {
	uint16 data;
	uint16 data1;

    TLG_NULLPTR_CHECK(state);
    TLG_NULLPTR_CHECK(ms);

    switch (state[0])
    {
    case TLG_STATE0:
#ifdef TLG_SUPPORT_RUNTIME_CHECK
    {uint32 version;
    TLG_GetChipVersion(base_addr, &version);}
#endif /* TLG_SUPPORT_RUNTIME_CHECK */
    TLG_CHIP_VERS_1_2_BEGIN
        #if defined(TLG_CMP_CHIP_1_3) || defined(TLG_CMP_CHIP_1_2)
        TLG_WriteReg(base_addr, 0x0,0x4012);
        TLG_ReadReg(base_addr,  REG_003D, &data);
        TLGHAL_SET(data,TLG_ON, REG_003D_BIT9_SHIFT,
                                REG_003D_BIT9_MASK);
        TLG_WriteReg(base_addr, REG_003D,data);
        #endif /* TLG_CMP_CHIP_1_2 */
    TLG_CHIP_VERS_1_1_ELSE
        #ifdef TLG_CMP_CHIP_1_1
        TLG_WriteReg(base_addr, 0x0,0x10);
        #endif /* TLG_CMP_CHIP_1_1 */
    TLG_CHIP_VERS_END
    TLG_WriteReg(base_addr, REG_0180,0xfffe);
    TLG_CHIP_VERS_1_2_BEGIN
        #if defined(TLG_CMP_CHIP_1_3) || defined(TLG_CMP_CHIP_1_2)
        TLG_WriteReg(base_addr, 0x181,0x0e1f);
        #endif /* TLG_CMP_CHIP_1_2 */
    TLG_CHIP_VERS_1_1_ELSE
        #ifdef TLG_CMP_CHIP_1_1
        TLG_WriteReg(base_addr, 0x181,0x0e3f);
        #endif /* TLG_CMP_CHIP_1_1 */
    TLG_CHIP_VERS_END
    state[0] = TLG_STATE1;
    *ms    = 5;
    break;

    case TLG_STATE1:
    TLG_WriteReg(base_addr, REG_0180,0xe81e);
    state[0] = TLG_STATE2;
    *ms    = 5;
    break;

    case TLG_STATE2:
    TLG_ReadReg(base_addr, REG_0198, &data1);
    TLGHAL_SET(data1, TLG_ON, REG_0198_BIT8_SHIFT, REG_0198_BIT8_MASK);
    TLG_WriteReg(base_addr, REG_0198, data1);
    TLG_WriteReg(base_addr, 0x197,0x04);
    TLG_WriteReg(base_addr, 0x03,0x2493);
    state[0] = TLG_STATE3;
    *ms    = 5;
    break;

    case TLG_STATE3:
    TLG_WriteReg(base_addr, REG_0180,0xe85e);
    TLG_WriteReg(base_addr, 0x197,0x0);
    TLG_WriteReg(base_addr, 0x1a7,0x0144);
    TLG_ReadReg(base_addr, REG_0198, &data1);
    TLGHAL_CLEAR(data1, REG_0198_BIT8_MASK);
    TLG_WriteReg(base_addr, REG_0198, data1);
    /* end of powerup calibration */
    TLG_WriteReg(base_addr, 0x18d,0x0081);
    TLG_WriteReg(base_addr, 0x036,0x30af);
    TLG_WriteReg(base_addr, 0x037,0xeed0);
    TLG_WriteReg(base_addr, 0x039,0x3f0);

    TLG_ReadReg(base_addr,      REG_0033, &data);
    TLGHAL_SET(data,            REG_0033_BIT11_8_VAL,
                                REG_0033_BIT11_8_SHIFT,
                                REG_0033_BIT11_8_MASK);
    TLG_WriteReg(base_addr,     REG_0033, data);

    TLG_ReadReg(base_addr,      REG_008C, &data);
    TLGHAL_SET(data, 0x84,      REG_008C_BIT15_8_SHIFT,
                                REG_008C_BIT15_8_MASK);
    TLGHAL_CLEAR(data,          REG_008C_BIT3_MASK);
    TLGHAL_CLEAR(data,          REG_008C_BIT2_0_MASK);
    TLG_WriteReg(base_addr,     REG_008C, data);

    TLG_ReadReg(base_addr,      REG_008D, &data);
    TLGHAL_SET(data, 1,         REG_008D_BIT9_SHIFT,
                                REG_008D_BIT9_MASK);
    TLGHAL_SET(data, 4,         REG_008D_BIT7_4_SHIFT,
                                REG_008D_BIT7_4_MASK);
    TLGHAL_SET(data, 10,        REG_008D_BIT3_0_SHIFT,
                                REG_008D_BIT3_0_MASK);
    TLG_WriteReg(base_addr,     REG_008D, data);

    state[0] = TLG_STATE4;
    *ms    = 5;
    break;

    case TLG_STATE4:
    state[0] = TLG_STATE_FINAL;
    *ms    = 0;
    break;

    default:
    break;
    }
    return(TLG_ERR_SUCCESS);
}

/*****************************************************************************
* TLG_ReInitFromDeepSleep
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_ReInitFromDeepSleep(uint32 base_addr) {
    tlg_statep  state;
    int         ms    = 0;

#ifndef TLG_EMBEDDED_TIMERS
    return(TLG_ERR_NOT_SUPPORTED);
#else
    state[0] = TLG_STATE1;
    do {
        TLG_InitASYNC(base_addr, state, &ms);
        if (ms)
            TLG_Delay((uint16)ms);
    } while (state[0] != TLG_STATE_FINAL);
    return(TLG_ERR_SUCCESS);
#endif /* TLG_EMBEDDED_TIMERS */
}

/*****************************************************************************
* TLG_GetYUVScale
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetYUVScale(uint32 base_addr, uint16 *y, uint16 *u, uint16 *v) {
    uint16 chromaScale;
    uint16 lumaScale;

    TLG_NULLPTR_CHECK(y);
    TLG_NULLPTR_CHECK(u);
    TLG_NULLPTR_CHECK(v);

    TLG_ReadReg(base_addr, REG_0068, &chromaScale);
    TLG_ReadReg(base_addr, REG_006D, &lumaScale);
    TLGHAL_GET(*v, chromaScale, REG_0068_BIT15_8_SHIFT,
                REG_0068_BIT15_8_MASK);
    TLGHAL_GET(*u, chromaScale, REG_0068_BIT7_0_SHIFT,
                REG_0068_BIT7_0_MASK);
    TLGHAL_GET(*y, lumaScale, REG_006D_BIT3_0_SHIFT,
                REG_006D_BIT3_0_MASK);
    return(TLG_ERR_SUCCESS);
}


/*****************************************************************************
* TLG_SetYUVScale
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetYUVScale(uint32 base_addr, uint16 y,uint16 u, uint16 v) {
    uint16 chromaScale;
    uint16 lumaScale;

    TLG_BOUNDS_CHECK(y, TLG_Y_MAX);
    TLG_BOUNDS_CHECK(u, TLG_U_MAX);
    TLG_BOUNDS_CHECK(v, TLG_V_MAX);

    TLG_ReadReg(base_addr, REG_0068, &chromaScale);
    TLG_ReadReg(base_addr, REG_006D, &lumaScale);
    TLGHAL_SET(chromaScale, v, REG_0068_BIT15_8_SHIFT,
                REG_0068_BIT15_8_MASK);
    TLGHAL_SET(chromaScale, u, REG_0068_BIT7_0_SHIFT,
                REG_0068_BIT7_0_MASK);
    TLGHAL_SET(lumaScale, y, REG_006D_BIT3_0_SHIFT,
                REG_006D_BIT3_0_MASK);
    TLG_WriteReg(base_addr, REG_0068, chromaScale);
    TLG_WriteReg(base_addr, REG_006D, lumaScale);

    return(TLG_ERR_SUCCESS);
}

/*****************************************************************************
* TLG_GetBWVideoMode
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetBWVideoMode(uint32 base_addr, uint16 *val) {
    uint16 videoConfig3;

    TLG_NULLPTR_CHECK(val);

    TLG_ReadReg(base_addr, REG_0070, &videoConfig3);
    TLGHAL_GET(*val, videoConfig3, REG_0070_BIT0_SHIFT,
            REG_0070_BIT0_MASK);
    return(TLG_ERR_SUCCESS);
}


/*****************************************************************************
* TLG_SetBWVideoMode
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetBWVideoMode(uint32 base_addr, uint16 val) {
    uint16 videoConfig3;

    TLG_BOUNDS_CHECK(val, TLG_ON);

    TLG_ReadReg(base_addr, REG_0070, &videoConfig3);
    TLGHAL_SET(videoConfig3, val, REG_0070_BIT0_SHIFT,
            REG_0070_BIT0_MASK);
    TLG_WriteReg(base_addr, REG_0070, videoConfig3);
    return(TLG_ERR_SUCCESS);
}

/*****************************************************************************
* TLG_GetVideoTestPatternState
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetVideoTestPatternState(uint32 base_addr, uint16 *val) {
    uint16 videoConfig3;
    uint16 videoConfig5;
    uint16 freezeFrame;
    uint16 useRom;

    TLG_NULLPTR_CHECK(val);

    /* determine test pattern state on basis of ff/favg and Rom */
    TLG_ReadReg(base_addr, REG_0072,  &videoConfig5);
    TLG_ReadReg(base_addr, REG_0070,  &videoConfig3);
    TLGHAL_GET(freezeFrame, videoConfig5, REG_0072_BIT0_SHIFT,
               REG_0072_BIT0_MASK);

    TLGHAL_GET(useRom, videoConfig3, REG_0070_BIT7_SHIFT,
               REG_0070_BIT7_MASK);

    *val = (freezeFrame == TLG_ON) && (useRom == TLG_ON);

    return(TLG_ERR_SUCCESS);
}


/*****************************************************************************
* TLG_SetVideoTestPatternState
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetVideoTestPatternState(uint32 base_addr, uint16 val) {
    uint16  videoConfig2,
            videoConfig3,
            videoConfig5,
            videoConfig6,
            videoConfig9,
            videoConfig10;

    TLG_ReadReg(base_addr, REG_0070,  &videoConfig3);
    TLG_ReadReg(base_addr, REG_0072,  &videoConfig5);
    TLG_ReadReg(base_addr, REG_0076,  &videoConfig9);
    TLG_ReadReg(base_addr, REG_0077, &videoConfig10);

    if (val == TLG_ON) {
        /* turn on Test Pattern: */
        TLG_ReadReg(base_addr, REG_006F,  &videoConfig2);
        TLG_ReadReg(base_addr, REG_0073,  &videoConfig6);

        /* turn off auto compensation, on ff */
        TLGHAL_CLEAR(videoConfig10, REG_0077_BIT12_MASK);
        TLGHAL_SET(videoConfig5, TLG_ON, REG_0072_BIT0_SHIFT,
                    REG_0072_BIT0_MASK);

        /* Turn on ff always reading (could be in ini) */
        TLGHAL_SET(videoConfig5, REG_0072_BIT6_5_FREEZE,
                    REG_0072_BIT6_5_SHIFT,
                    REG_0072_BIT6_5_MASK);

        /* turn off ff aging (could be in ini) */
        TLGHAL_CLEAR(videoConfig6, REG_0073_BIT15_MASK);

        /* Enforce min off time (could be in ini) */
        TLGHAL_SET(videoConfig2, TLG_ON, REG_006F_BIT6_SHIFT,
                    REG_006F_BIT6_MASK);

        /*  turn on enforce ff min width fill (could be in ini) */
        TLGHAL_SET(videoConfig3, TLG_ON, REG_0070_BIT15_SHIFT,
                    REG_0070_BIT15_MASK);

        /* turn off use external counters */
        TLGHAL_CLEAR(videoConfig9, REG_0076_BIT7_MASK);

        /* turn on use ROM */
        TLGHAL_SET(videoConfig3, TLG_ON, REG_0070_BIT7_SHIFT,
                    REG_0070_BIT7_MASK);

        TLG_WriteReg(base_addr, REG_006F, videoConfig2);
        TLG_WriteReg(base_addr, REG_0070, videoConfig3);
        TLG_WriteReg(base_addr, REG_0073, videoConfig6);
    } else {
        /* turn off Test Pattern:
         * turn off use ROM
         */
        TLGHAL_CLEAR(videoConfig3, REG_0070_BIT7_MASK);

         /* turn on auto compensation, off ff */
       TLGHAL_CLEAR(videoConfig5, REG_0072_BIT0_MASK);
       TLGHAL_SET(videoConfig10, TLG_ON, REG_0077_BIT12_SHIFT,
                    REG_0077_BIT12_MASK);

        /* turn on use external counters */
        TLGHAL_SET(videoConfig9, TLG_ON, REG_0076_BIT7_SHIFT,
                    REG_0076_BIT7_MASK);

    }
    TLG_WriteReg(base_addr, REG_0070,  videoConfig3);
    TLG_WriteReg(base_addr, REG_0072,  videoConfig5);
    TLG_WriteReg(base_addr, REG_0076,  videoConfig9);
    TLG_WriteReg(base_addr, REG_0077, videoConfig10);
    return(TLG_ERR_SUCCESS);
}

/*****************************************************************************
* TLG_Get601VideoOutClock
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_Get601VideoOutClock(uint32 base_addr, uint16 *val) {
    uint16 videoConfig3;

    TLG_NULLPTR_CHECK(val);

    TLG_ReadReg(base_addr, REG_0070, &videoConfig3);
    TLGHAL_GET(*val, videoConfig3, REG_0070_BIT4_SHIFT,
            REG_0070_BIT4_MASK);
    return(TLG_ERR_SUCCESS);
}


/*****************************************************************************
* TLG_Set601VideoOutClock
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_Set601VideoOutClock(uint32 base_addr, uint16 val) {
    uint16 videoConfig3;

    TLG_BOUNDS_CHECK(val, TLG_INVERT);

    TLG_ReadReg(base_addr, REG_0070, &videoConfig3);
    TLGHAL_SET(videoConfig3, val, REG_0070_BIT4_SHIFT,
            REG_0070_BIT4_MASK);
    TLG_WriteReg(base_addr, REG_0070, videoConfig3);
    return(TLG_ERR_SUCCESS);
}


/*****************************************************************************
* TLG_GetChromaLumaOrder
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_GetChromaLumaOrder(uint32 base_addr, uint16 *val) {
    uint16 videoConfig2;

    TLG_NULLPTR_CHECK(val);

    TLG_ReadReg(base_addr, REG_006F, &videoConfig2);
    TLGHAL_GET(*val, videoConfig2, REG_006F_BIT4_SHIFT,
            REG_006F_BIT4_MASK);
    return(TLG_ERR_SUCCESS);
}


/*****************************************************************************
* TLG_SetChromaLumaOrder
*
*
*
*
*****************************************************************************/
TLGDLL_API int TLG_SetChromaLumaOrder(uint32 base_addr, uint16 val) {
    uint16 videoConfig2;

    TLG_BOUNDS_CHECK(val, TLG_CHRLUM_SWAP);

    TLG_ReadReg(base_addr, REG_006F, &videoConfig2);
    TLGHAL_SET(videoConfig2, val, REG_006F_BIT4_SHIFT,
            REG_006F_BIT4_MASK);
    TLG_WriteReg(base_addr, REG_006F, videoConfig2);
    return(TLG_ERR_SUCCESS);
}