📄 tlg1100hal.h
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#define REG_0070_BIT6_5_MASK (BIT6|BIT5)
#define REG_0070_BIT6_5_SHIFT (5)
#define REG_0070_BIT4_MASK (BIT4)
#define REG_0070_BIT4_SHIFT (4)
#define REG_0070_BIT2_MASK (BIT2)
#define REG_0070_BIT2_SHIFT (2)
#define REG_0070_BIT0_MASK (BIT0)
#define REG_0070_BIT0_SHIFT (0)
#define REG_0070_DEFAULT_VALUE (0x8634)
#define REG_0071 (0x0071)
#define REG_0071_BIT9_8_MASK (BIT9|BIT8)
#define REG_0071_BIT9_8_SHIFT (8)
#define REG_0071_DEFAULT_VALUE (0x8c6a)
#define REG_0071_BIT7_4_MASK (BIT7_4)
#define REG_0071_BIT7_4_SHIFT (4)
#define REG_0072 (0x0072)
#define REG_0072_BIT6_5_MASK (BIT6|BIT5)
#define REG_0072_BIT6_5_SHIFT (5)
#define REG_0072_BIT6_5_FREEZE (3)
#define REG_0072_BIT6_5_UNFREEZE (2)
#define REG_0072_BIT6_5_AUTO (0)
#define REG_0072_BIT0_MASK (BIT0)
#define REG_0072_BIT0_SHIFT (0)
#define REG_0073 (0x0073)
#define REG_0073_BIT15_MASK (BIT15)
#define REG_0073_BIT15_SHIFT (15)
#define REG_0076 (0x0076)
#define REG_0076_BIT7_MASK (BIT7)
#define REG_0076_BIT7_SHIFT (7)
#define REG_0077 (0x0077)
#define REG_0077_BIT12_MASK (BIT12)
#define REG_0077_BIT12_SHIFT (12)
#define REG_0077_BIT5_0_MASK (BIT5_0)
#define REG_0077_BIT5_0_SHIFT (0)
#define REG_0078 (0x0078)
#define REG_0078_BIT15_MASK (BIT15)
#define REG_0078_BIT15_SHIFT (15)
#define REG_0078_BIT14_MASK (BIT14)
#define REG_0078_BIT14_SHIFT (14)
#define REG_0078_BIT6_MASK (BIT6)
#define REG_0078_BIT6_SHIFT (6)
#define REG_0078_BIT1_MASK (BIT1)
#define REG_0078_BIT1_SHIFT (1)
#define REG_0078_BIT0_MASK (BIT0)
#define REG_0078_BIT0_SHIFT (0)
#define REG_007F (0x007f)
#define REG_007F_BIT15_0_MASK (BITS15_0)
#define REG_007F_BIT15_0_SHIFT (0)
#define REG_0080 (0x0080)
#define REG_0080_BIT15_0_MASK (BITS15_0)
#define REG_0080_BIT15_0_SHIFT (0)
#define REG_0081 (0x0081)
#define REG_0081_BIT15_0_MASK (BITS15_0)
#define REG_0081_BIT15_0_SHIFT (0)
#define REG_0082 (0x0082)
#define REG_0082_BIT15_0_MASK (BITS15_0)
#define REG_0082_BIT15_0_SHIFT (0)
#define REG_0083 (0x0083)
#define REG_0083_BIT15_0_MASK (BITS15_0)
#define REG_0083_BIT15_0_SHIFT (0)
#define REG_0084 (0x0084)
#define REG_0084_BIT15_0_MASK (BITS15_0)
#define REG_0084_BIT15_0_SHIFT (0)
#define REG_0085 (0x0085)
#define REG_0085_BIT15_0_MASK (BITS15_0)
#define REG_0085_BIT15_0_SHIFT (0)
#define REG_0086 (0x0086)
#define REG_0086_BIT15_0_MASK (BITS15_0)
#define REG_0086_BIT15_0_SHIFT (0)
#define REG_0087 (0x0087)
#define REG_0087_BIT15_0_MASK (BITS15_0)
#define REG_0087_BIT15_0_SHIFT (0)
#define REG_0088 (0x0088)
#define REG_0088_BIT15_0_MASK (BITS15_0)
#define REG_0088_BIT15_0_SHIFT (0)
#define REG_0089 (0x0089)
#define REG_0089_BIT15_0_MASK (BITS15_0)
#define REG_0089_BIT15_0_SHIFT (0)
#define REG_008A (0x008a)
#define REG_008A_BIT15_0_MASK (BITS15_0)
#define REG_008A_BIT15_0_SHIFT (0)
#define REG_008B (0x008b)
#define REG_008B_BIT8_MASK (BIT8)
#define REG_008B_BIT8_SHIFT (8)
#define REG_008B_BIT7_6_MASK (BIT7|BIT6)
#define REG_008B_BIT7_6_SHIFT (6)
#define REG_008B_BIT5_4_MASK (BIT5|BIT4)
#define REG_008B_BIT5_4_SHIFT (4)
#define REG_008B_BIT3_MASK (BIT3)
#define REG_008B_BIT3_SHIFT (3)
#define REG_008B_BIT1_MASK (BIT1)
#define REG_008B_BIT1_SHIFT (1)
#define REG_008B_BIT0_MASK (BIT0)
#define REG_008B_BIT0_SHIFT (0)
#define REG_008C (0x008c)
#define REG_008C_BIT15_8_MASK (BIT15_8)
#define REG_008C_BIT15_8_SHIFT (8)
#define REG_008C_BIT7_MASK (BIT7)
#define REG_008C_BIT7_SHIFT (7)
#define REG_008C_BIT6_4_MASK (BIT6|BIT5|BIT4)
#define REG_008C_BIT6_4_SHIFT (4)
#define REG_008C_BIT3_MASK (BIT3)
#define REG_008C_BIT3_SHIFT (3)
#define REG_008C_BIT2_0_MASK (BIT2|BIT1|BIT0)
#define REG_008C_BIT2_0_SHIFT (0)
#define REG_008D (0x008d)
#define REG_008D_MASK (0x03FF)
#define REG_008D_BIT9_MASK (BIT9)
#define REG_008D_BIT9_SHIFT (9)
#define REG_008D_BIT8_MASK (BIT8)
#define REG_008D_BIT8_SHIFT (8)
#define REG_008D_BIT7_4_MASK (BIT7_4)
#define REG_008D_BIT7_4_SHIFT (4)
#define REG_008D_BIT3_0_MASK (BIT3_0)
#define REG_008D_BIT3_0_SHIFT (0)
#define REG_008E (0x008e)
#define REG_008E_BIT7_0_MASK (BIT7_0)
#define REG_008E_BIT7_0_SHIFT (0)
#define REG_008F (0x008f)
#define REG_008F_BIT0_MASK (BIT0)
#define REG_008F_BIT0_SHIFT (0)
#define REG_0095 (0x0095)
#define REG_0095_BIT7_1_MASK (BIT7_4|BIT3|BIT2|BIT1)
#define REG_0095_BIT7_1_SHIFT (1)
#define REG_0095_BIT0_MASK (BIT0)
#define REG_0095_BIT0_SHIFT (0)
#define REG_0096 (0x0096)
#define REG_0096_BIT12_8_MASK (BIT12|BIT11_8)
#define REG_0096_BIT12_8_SHIFT (8)
#define REG_0096_BIT5_0_MASK (BIT5|BIT4|BIT3_0)
#define REG_0096_BIT5_0_SHIFT (0)
#define REG_0097 (0x0097)
#define REG_0097_BIT5_4_MASK (BIT5|BIT4)
#define REG_0097_BIT5_4_SHIFT (4)
#define REG_0097_BIT1_MASK (BIT1)
#define REG_0097_BIT1_SHIFT (1)
#define REG_0097_BIT0_MASK (BIT0)
#define REG_0097_BIT0_SHIFT (0)
#define REG_0098 (0x0098)
#define REG_0098_BIT3_0_MASK (BIT3_0)
#define REG_0098_BIT3_0_SHIFT (0)
#define REG_0098_BIT3_0_ADC (2)
#define REG_009D (0x009d)
#define REG_009D_BIT3_1_MASK (BIT3|BIT2|BIT1)
#define REG_009D_BIT3_1_SHIFT (1)
#define REG_009E (0x009e)
#define REG_009E_BIT3_1_MASK (BIT3|BIT2|BIT1)
#define REG_009E_BIT3_1_SHIFT (1)
#define REG_0100 (0x0100)
#define REG_0100_BIT11_0_MASK (BIT11_0)
#define REG_0100_BIT11_0_SHIFT (0)
#define REG_010B (0x010b)
#define REG_010D (0x010d)
#define REG_010D_BIT15_10_MASK (BIT15_12|BIT11|BIT10)
#define REG_010D_BIT15_10_SHIFT (10)
#define REG_010E (0x010e)
#define REG_010E_BIT15_11_MASK (BIT15_12|BIT11)
#define REG_010E_BIT15_11_SHIFT (11)
#define REG_0111 (0x0111)
#define REG_0111_BIT7_3_MASK (BIT7_4|BIT3)
#define REG_0111_BIT7_3_SHIFT (3)
#define REG_0111_BIT7_4_MASK (BIT7_4)
#define REG_0111_BIT7_4_SHIFT (4)
#define REG_0113 (0x0113)
#define REG_0113_BIT1_0_MASK (BIT1|BIT0)
#define REG_0113_BIT1_0_SHIFT (0)
#define REG_0114 (0x0114)
#define REG_0114_BIT12_9_MASK (BIT12_9)
#define REG_0114_BIT12_9_SHIFT (9)
#define REG_0115 (0x0115)
#define REG_011C (0x011c)
#define REG_0120 (0x0120)
#define REG_0120_BIT11_0_MASK (BIT11_0)
#define REG_0120_BIT11_0_SHIFT (0)
#define REG_0123 (0x0123)
#define REG_0129 (0x0129)
#define REG_0132 (0x0132)
#define REG_0139 (0x0139)
#define REG_0139_BIT10_9_MASK (BIT10|BIT9)
#define REG_0139_BIT10_9_SHIFT (9)
#define REG_013B (0x013b)
#define REG_013B_BIT6_MASK (BIT6)
#define REG_013B_BIT5_MASK (BIT5)
#define REG_013B_BIT5_SHIFT (5)
#define REG_013B_BIT4_MASK (BIT4)
#define REG_013B_BIT3_MASK (BIT3)
#define REG_013B_BIT3_SHIFT (3)
#define REG_013B_BIT2_MASK (BIT2)
#define REG_013B_BIT1_MASK (BIT1)
#define REG_013B_BIT0_MASK (BIT0)
#define REG_013B_BIT6_0_MASK (BIT6|BIT5|BIT4|BIT3_0)
#define REG_013B_BIT6_0_SHIFT (0)
#define REG_0180 (0x0180)
#define REG_0180_BIT15_13_MASK (BIT13|BIT14|BIT15)
#define REG_0180_BIT15_13_SHIFT (13)
#define REG_0181 (0x0181)
#define REG_0184 (0x0184)
#define REG_0184_BIT9_MASK (BIT9)
#define REG_0184_BIT9_SHIFT (9)
#define REG_0184_BIT8_0_MASK (BIT8|BIT7_0)
#define REG_0184_BIT8_0_SHIFT (0)
#define REG_0185 (0x0185)
#define REG_0185_BIT11_9_MASK (BIT9|BIT10|BIT11)
#define REG_0185_BIT11_9_SHIFT (9)
#define REG_0186 (0x0186)
#define REG_0186_BIT3_0_MASK (BIT3_0)
#define REG_0186_BIT3_0_SHIFT (0)
#define REG_0187 (0x0187)
#define REG_0187_BIT14_10_MASK (BIT14_10)
#define REG_0187_BIT14_10_SHIFT (10)
#define REG_0187_BIT9_MASK (BIT9)
#define REG_0187_BIT9_SHIFT (9)
#define REG_0187_BIT8_0_MASK (BIT8|BIT7_0)
#define REG_0187_BIT8_0_SHIFT (0)
#define REG_0188 (0x0188)
#define REG_0188_BIT11_9_MASK (BIT9|BIT10|BIT11)
#define REG_0188_BIT11_9_SHIFT (9)
#define REG_0189 (0x0189)
#define REG_0189_BIT6_MASK (BIT6)
#define REG_0189_BIT6_SHIFT (6)
#define REG_0189_BIT5_MASK (BIT5)
#define REG_0189_BIT5_SHIFT (5)
#define REG_0189_BIT3_0_MASK (BIT3_0)
#define REG_0189_BIT3_0_SHIFT (0)
#define REG_018A (0x018a)
#define REG_018A_BIT14_10_MASK (BIT14_10)
#define REG_018A_BIT14_10_SHIFT (10)
#define REG_018A_BIT9_MASK (BIT9)
#define REG_018A_BIT9_SHIFT (9)
#define REG_018A_BIT8_0_MASK (BIT8|BIT7_0)
#define REG_018A_BIT8_0_SHIFT (0)
#define REG_018B (0x018b)
#define REG_018B_BIT11_9_MASK (BIT9|BIT10|BIT11)
#define REG_018B_BIT11_9_SHIFT (9)
#define REG_018D (0x018d)
#define REG_018D_BIT15_MASK (BIT15)
#define REG_018D_BIT7_MASK (BIT7)
#define REG_018D_CAL_SETTING (REG_018D_BIT15_MASK \
|REG_018D_BIT7_MASK \
|REG_018D_BIT0_MASK)
#define REG_018D_BIT0_MASK (BIT0)
#define REG_018E (0x018e)
#define REG_018E_BIT15_12_MASK (BIT15_12)
#define REG_018E_BIT15_12_SHIFT (12)
#define REG_018E_BIT11_8_MASK (BIT11_8)
#define REG_018E_BIT11_8_SHIFT (8)
#define REG_018E_NOREV (0xf)
#define REG_018F (0x018f)
#define REG_018F_BIT5_MASK (BIT5)
#define REG_018F_BIT5_SHIFT (5)
#define REG_0193 (0x0193)
#define REG_0193_BIT15_MASK (BIT15)
#define REG_0193_BIT15_SHIFT (15)
#define REG_0198 (0x0198)
#define REG_0198_BIT8_MASK (BIT8)
#define REG_0198_BIT8_SHIFT (8)
#define REG_01A5 (0x01a5)
#define REG_01A6 (0x01a6)
#define REG_01A7 (0x01a7)
#define REG_01A7_BIT8_MASK (BIT8)
#define REG_01A8 (0x01a8)
#define REG_01A8_BIT11_9_MASK (BIT11_9)
#define REG_01A8_BIT11_9_SHIFT (9)
#define REG_01B0 (0x01b0)
#define REG_01B0_BIT12_MASK (BIT12)
#define REG_01B0_BIT12_SHIFT (12)
#define REG_01B0_BIT6_0_MASK (BIT6_0)
#define REG_01B0_BIT6_0_SHIFT (0)
#define REG_01B2 (0x01b2)
#define REG_01B3 (0x01b3)
#define REG_01B3_VALUE_MASK (0x3fff)
#endif /* TLG_CHIP_TYPE */
#endif /* _TLG1100HAL_H_ */
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