📄 tlg1100hal.h
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#ifndef _TLG1100HAL_H_
#define _TLG1100HAL_H_
/****************************************************************************/
/*!@file TLG1100Hal.h
*
* @brief Hardware Definitions for the TLGHAL programmatic interface support.
*
* This file contains the api definitions for the TLGHAL Ultra Low Power
* NTSC/PAL Tuner/Decoder chip support library.
*
*
****************************************************************************/
/* Revision Information:
*
* $Revision: 1.28 $
*
* (c) 2006 Telegent Systems
****************************************************************************/
#include "tlgConfig.h"
#if TLG_CHIP_TYPE == TLG_CHIP_TYPE_TLG1100_1
#define BIT0 ((unsigned short)0x0001) /*!< bit 0 */
#define BIT1 ((unsigned short)0x0002) /*!< bit 1 */
#define BIT2 ((unsigned short)0x0004) /*!< bit 2 */
#define BIT3 ((unsigned short)0x0008) /*!< bit 3 */
#define BIT4 ((unsigned short)0x0010) /*!< bit 4 */
#define BIT5 ((unsigned short)0x0020) /*!< bit 5 */
#define BIT6 ((unsigned short)0x0040) /*!< bit 6 */
#define BIT7 ((unsigned short)0x0080) /*!< bit 7 */
#define BIT8 ((unsigned short)0x0100) /*!< bit 8 */
#define BIT9 ((unsigned short)0x0200) /*!< bit 9 */
#define BIT10 ((unsigned short)0x0400) /*!< bit 10 */
#define BIT11 ((unsigned short)0x0800) /*!< bit 11 */
#define BIT12 ((unsigned short)0x1000) /*!< bit 12 */
#define BIT13 ((unsigned short)0x2000) /*!< bit 13 */
#define BIT14 ((unsigned short)0x4000) /*!< bit 14 */
#define BIT15 ((unsigned short)0x8000) /*!< bit 15 */
#define BIT3_0 ((unsigned short)0x000f)
#define BIT7_4 ((unsigned short)0x00f0)
#define BIT11_8 ((unsigned short)0x0f00)
#define BIT15_12 ((unsigned short)0xf000)
#define BIT7_0 (BIT7_4|BIT3_0)
#define BIT15_8 (BIT15_12|BIT11_8)
#define BIT15_0 (BIT15_8|BIT7_0)
#define BIT11_0 (BIT11_8|BIT7_0)
#define BIT14_10 (BIT14|BIT13|BIT12|BIT11|BIT10)
#define BIT6_0 (BIT6|BIT5|BIT4|BIT3_0)
#define BIT5_0 (BIT5|BIT4|BIT3_0)
#define BIT11_9 (BIT11|BIT10|BIT9)
#define BIT12_9 (BIT12|BIT11_9)
/** Clear a masked area in a register value */
#define TLGHAL_CLEAR(reg, mask) reg &= ((uint16) ~(mask))
/** Set a masked area to a value */
#define TLGHAL_SET(reg, var, shift, mask) \
reg = ((uint16) (((reg) & ~(mask)) | (((var) << (shift)) & (mask))))
/** Get a field in a register */
#define TLGHAL_GET(var, reg, shift, mask) var = (((reg) & (mask)) >> (shift))
/******************************************************************************
* TLG1100 CHIP REVISION CONTROL DEFINES
******************************************************************************/
/*
* Chip Version Configuration Section
*/
/*****************************************************************************
* CHIP CONFIG CONSTANTS
*
* The following are chip version configuration constants and should not be
* changed.
*****************************************************************************/
#define TLG_CHIP_TYPE_MASK (0xffff0000)
#define TLG_CHIP_TYPE_SHIFT (16)
#define TLG_CHIP_REV_MASK (0x0000ff00)
#define TLG_CHIP_REV_SHIFT (8)
#define TLG_CHIP_PATCH_MASK (0x000000ff)
#define TLG_CHIP_PATCH_SHIFT (0)
#define TLG_CHIP_VER_CFG(t, r) ( ((t) << TLG_CHIP_TYPE_SHIFT) \
| ((r) << TLG_CHIP_REV_SHIFT))
#define TLG1100_VERS_1_1 \
TLG_CHIP_VER_CFG(TLG_CHIP_TYPE_TLG1100_1,TLG_CHIP_REV_1)
#define TLG1100_VERS_1_2 \
TLG_CHIP_VER_CFG(TLG_CHIP_TYPE_TLG1100_1,TLG_CHIP_REV_2)
#define TLG1100_VERS_1_3 \
TLG_CHIP_VER_CFG(TLG_CHIP_TYPE_TLG1100_1,TLG_CHIP_REV_3)
#define TLG1150_VERS_1_1 \
TLG_CHIP_VER_CFG(TLG_CHIP_TYPE_TLG1150_1,TLG_CHIP_REV_1)
#define TLG_NO_VERS (TLG_CHIP_TYPE_MASK|TLG_CHIP_REV_MASK)
/** Chip version configuration.
*
* TLG_CHIP_VERS defines the latest type and version of chip that the current
* code compile will support. It uses the defines TLG_CHIP_TYPE and
* TLG_CHIP_REV which are declared in tlg1100Config.h.
*
*/
#define TLG_CHIP_VERS TLG_CHIP_VER_CFG(TLG_CHIP_TYPE, TLG_CHIP_REV)
#define TLG_CHIP_CMP_GE(v) \
( (((v) & TLG_CHIP_TYPE_MASK) >> TLG_CHIP_TYPE_SHIFT) == TLG_CHIP_TYPE \
&& (((v) & TLG_CHIP_REV_MASK) >> TLG_CHIP_REV_SHIFT) >= TLG_CHIP_REV)
#define TLG_CHIP_CMP_EQ(v) \
( (((v) & TLG_CHIP_TYPE_MASK) >> TLG_CHIP_TYPE_SHIFT) == TLG_CHIP_TYPE \
&& (((v) & TLG_CHIP_REV_MASK) >> TLG_CHIP_REV_SHIFT) == TLG_CHIP_REV)
#if !TLG_CHIP_CMP_EQ(TLG1100_VERS_1_2) && !TLG_CHIP_CMP_EQ(TLG1100_VERS_1_1) && !TLG_CHIP_CMP_EQ(TLG1100_VERS_1_3) && !TLG_CHIP_CMP_EQ(TLG1150_VERS_1_1)
ERROR! UNSUPPORTED CHIP VERSION
#endif
/** Compile in code to support TLG1150 1.1.
*/
#if defined(TLG_SUPPORT_RUNTIME_CHECK) || TLG_CHIP_CMP_EQ(TLG1150_VERS_1_1)
#define TLG_CMP_CHIP_1150_1_1 (1)
#endif /* TLG_CMP_CHIP_1150_1_1 */
/** Compile in code to support TLG1100 1.3.
*/
#if defined(TLG_SUPPORT_RUNTIME_CHECK) || TLG_CHIP_CMP_EQ(TLG1100_VERS_1_3)
#define TLG_CMP_CHIP_1_3 (1)
#endif /* TLG_CMP_CHIP_1_3 */
/** Compile in code to support TLG1100 1.2.
*/
#if defined(TLG_SUPPORT_RUNTIME_CHECK) || TLG_CHIP_CMP_EQ(TLG1100_VERS_1_2)
#define TLG_CMP_CHIP_1_2 (1)
#endif /* TLG_CMP_CHIP_1_2 */
/** Compile in code to support TLG1100 1.1
*/
#if defined(TLG_SUPPORT_RUNTIME_CHECK) || TLG_CHIP_CMP_EQ(TLG1100_VERS_1_1)
#define TLG_CMP_CHIP_1_1 (1)
#endif /* TLG_CMP_CHIP_1_1 */
/*
* TLGHAL_REGNAME (reg addr)
*
* TLGHAL_REGNAME_FIELDNAME_MASK (bits that define field)
*
* TLGHAL_REGNAME_FIELDNAME_SHIFT (least significant bit in field. Number
* of bits to shift to normalize field
* value)
*
* TLGHAL_REGNAME_DEFAULT_VALUE (initialization value for register)
*/
#define REG_0000 (0x0000)
#define REG_0000_BIT7_MASK (BIT7)
#define REG_0000_BIT7_SHIFT (7)
#define REG_0000_BIT6_MASK (BIT6)
#define REG_0000_BIT6_SHIFT (6)
#define REG_0000_BIT5_MASK (BIT5)
#define REG_0000_BIT5_SHIFT (5)
#define REG_0000_BIT2_MASK (BIT2)
#define REG_0000_BIT2_SHIFT (2)
#define REG_0000_BIT1_MASK (BIT1)
#define REG_0000_BIT1_SHIFT (1)
#define REG_0000_BIT0_MASK (BIT0)
#define REG_0000_BIT0_SHIFT (0)
#define REG_0001 (0x0001)
#define REG_0001_BIT0_MASK (BIT0)
#define REG_0001_BIT0_SHIFT (0)
#define REG_0002 (0x0002)
#define REG_0002_BIT3_0_MASK (BIT3_0)
#define REG_0002_BIT3_0_SHIFT (0)
#define REG_0004 (0x0004)
#define REG_0004_BIT12_MASK (BIT12)
#define REG_0004_BIT12_SHIFT (12)
#define REG_000F (0x000f)
#define REG_000F_BIT12_MASK (BIT12)
#define REG_000F_BIT12_SHIFT (12)
#define REG_001B (0x001b)
#define REG_001C (0x001c)
#define REG_001D (0x001d)
#define REG_0021 (0x0021)
#define REG_0021_BIT14_10_MASK (BIT14_10)
#define REG_0021_BIT14_10_SHIFT (10)
#define FILT_FORCE_FC_VAL (0x4000)
#define FILT_FC_F3P0 (0x0020)
#define FILT_FC_F2P5 (0x0001)
#define REG_0022 (0x0022)
#define EDGE_CNT_FORCE_VAL_8 (0x0364)
#define EDGE_CNT_FORCE_VAL_6 (0x0485)
#define EDGE_CNT_FORCE_VAL_5 (0x056d)
#define REG_0022_BIT12_MASK (BIT12)
#define REG_0022_BIT12_SHIFT (12)
#define REG_0022_BIT10_0_MASK (BIT10|BIT9|BIT8|BIT7_0)
#define REG_0022_BIT10_0_SHIFT (0)
#define REG_002E (0x002e)
#define REG_002F (0x002f)
#define REG_0030 (0x0030)
#define REG_0033 (0x0033)
#define REG_0033_BIT12_MASK (BIT12)
#define REG_0033_BIT12_SHIFT (12)
#define REG_0033_BIT11_8_MASK (BIT11|BIT10|BIT9|BIT8)
#define REG_0033_BIT11_8_SHIFT (8)
#define REG_0033_BIT11_8_VAL (0xd)
#define REG_0036 (0x0036)
#define REG_0036_BIT3_1_MASK (BIT1|BIT2|BIT3)
#define REG_0036_BIT3_1_SHIFT (1)
#define REG_0036_BIT15_9_MASK (BIT9|BIT10|BIT11|BIT15_12)
#define REG_0036_BIT15_9_SHIFT (9)
#define REG_0036_BIT7_6_MASK (BIT6|BIT7)
#define REG_0036_BIT7_6_SHIFT (6)
#define REG_0037 (0x0037)
#define REG_0037_BIT9_MASK (BIT9)
#define REG_0037_BIT9_SHIFT (9)
#define REG_0037_BIT12_10_MASK (BIT10|BIT11|BIT12)
#define REG_0037_BIT12_10_SHIFT (10)
#define REG_0038 (0x0038)
#define REG_0039 (0x0039)
#define REG_003A (0x003a)
#define REG_003A_BIT13_MASK (BIT13)
#define REG_003A_BIT13_SHIFT (13)
#define REG_003A_BIT9_0_MASK (BIT9|BIT8|BIT7_0)
#define REG_003A_BIT9_0_SHIFT (0)
#define REG_003D (0x003d)
#define REG_003D_BIT4_MASK (BIT4)
#define REG_003D_BIT4_SHIFT (4)
#define REG_003D_BIT7_MASK (BIT7)
#define REG_003D_BIT7_SHIFT (7)
#define REG_003D_BIT9_MASK (BIT9)
#define REG_003D_BIT9_SHIFT (9)
#define REG_004A (0x004a)
#define REG_004A_BIT6_4_MASK (BIT6|BIT5|BIT4)
#define REG_004A_BIT6_4_SHIFT (4)
#define REG_004A_BIT1_MASK (BIT1)
#define REG_004A_BIT1_SHIFT (1)
#define REG_004A_BIT0_MASK (BIT0)
#define REG_004A_BIT0_SHIFT (0)
#define REG_004B (0x004b)
#define REG_004B_BIT15_MASK (BIT15)
#define REG_004B_BIT15_SHIFT (15)
#define REG_004B_BIT14_0_MASK (BIT14|BIT13|BIT12|BIT11_0)
#define REG_004B_BIT14_0_SHIFT (0)
#define REG_0053 (0x0053)
#define REG_0053_BIT14_12_MASK (BIT14|BIT13|BIT12)
#define REG_0053_BIT14_12_SHIFT (12)
#define REG_0054 (0x0054)
#define REG_0054_BIT15_MASK (BIT15)
#define REG_0054_BIT15_SHIFT (15)
#define REG_0054_BIT12_MASK (BIT12)
#define REG_0054_BIT12_SHIFT (12)
#define REG_0068 (0x0068)
#define REG_0068_BIT15_8_MASK (BIT15_8)
#define REG_0068_BIT15_8_SHIFT (8)
#define REG_0068_BIT7_0_MASK (BIT7_0)
#define REG_0068_BIT7_0_SHIFT (0)
#define REG_006C (0x006c)
#define REG_006C_BIT9_MASK (BIT9)
#define REG_006C_BIT9_SHIFT (9)
#define REG_006C_BIT8_MASK (BIT8)
#define REG_006C_BIT8_SHIFT (8)
#define REG_006D (0x006d)
#define REG_006D_BIT3_0_MASK (BIT3_0)
#define REG_006D_BIT3_0_SHIFT (0)
#define REG_006F (0x006f)
#define REG_006F_BIT6_MASK (BIT6)
#define REG_006F_BIT6_SHIFT (6)
#define REG_006F_BIT4_MASK (BIT4)
#define REG_006F_BIT4_SHIFT (4)
#define REG_0070 (0x0070)
#define REG_0070_BIT15_MASK (BIT15)
#define REG_0070_BIT15_SHIFT (15)
#define REG_0070_BIT7_MASK (BIT7)
#define REG_0070_BIT7_SHIFT (7)
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