os_isr.s

凌阳SPCE3200多媒体开发板自带源程序。共安排了32个子目录

#include "os_isr.h"
	.section .exception_vec,"ax" 
	/*.global norm_debug_vec*/
	/*.text*/
	# Normal debug exception vector
.align 2	
norm_debug_vec:
	j	norm_debug_service

	# General exception vector
.align 2	
general_vec:
	j	general_service

	# Hardware interrupt exception vector (1~63)
.align 2
int1_vec:
	j	int_service
.align 2
int2_vec:
	j	int_service
.align 2
int3_vec:
	j	int_service
.align 2
int4_vec:
	j	int_service
.align 2
int5_vec:
	j	int_service
.align 2
int6_vec:
	j	int_service
.align 2
int7_vec:
	j	int_service
.align 2
int8_vec:
	j	int_service
.align 2
int9_vec:
	j	int_service
.align 2
int10_vec:
	j	int_service
.align 2
int11_vec:
	j	int_service
.align 2
int12_vec:
	j	int_service
.align 2
int13_vec:
	j	int_service
.align 2
int14_vec:
	j	int_service
.align 2
int15_vec:
	j	int_service
.align 2
int16_vec:
	j	int_service
.align 2
int17_vec:
	j	int_service
.align 2
int18_vec:
	j	int_service
.align 2
int19_vec:
	j	int_service
.align 2
int20_vec:
	j	int_service
.align 2
int21_vec:
	j	int_service
.align 2
int22_vec:
	j	save_reg
.align 2
int23_vec:
	j	save_reg
.align 2
int24_vec:
	j	save_reg
.align 2
int25_vec:
	j	int_service
.align 2
int26_vec:
	j	save_reg
.align 2
int27_vec:	
	j	save_reg
.align 2
int28_vec:
	#j	int_service
	j	save_reg
.align 2
int29_vec:
	j	save_reg
.align 2
int30_vec:
	#j	int_service
	j save_reg
.align 2
int31_vec:
	j	int_service
.align 2
int32_vec:
	j	save_reg
.align 2
int33_vec:
	j	save_reg
.align 2
int34_vec:
	j	int_service
.align 2
int35_vec:
	j	int_service
.align 2
int36_vec:
	j	int_service
.align 2
int37_vec:
	j	save_reg
.align 2
int38_vec:
	j	save_reg
.align 2
int39_vec:
	j	save_reg
.align 2
int40_vec:
	j	save_reg
.align 2
int41_vec:
	j	int_service
.align 2
int42_vec:
	j	int_service
.align 2
int43_vec:
	#j	int_service
	j	save_reg
.align 2
int44_vec:
	j	int_service
.align 2
int45_vec:
	j	int_service
.align 2
int46_vec:
	j	save_reg	
.align 2
int47_vec:
	j	save_reg
.align 2
int48_vec:
	j	save_reg
.align 2
int49_vec:
	j	save_reg
.align 2
int50_vec:
	j	save_reg
.align 2
int51_vec:
	j	save_reg
.align 2
int52_vec:
	j	save_reg
.align 2
int53_vec:
	j	save_reg
.align 2
int54_vec:
	#j	int_service
	j	save_reg
.align 2
int55_vec:	
	j	save_reg
.align 2
int56_vec:
	j	save_reg
.align 2
int57_vec:
	j	int_service
.align 2
int58_vec:
	j	int_service
.align 2
int59_vec:
	j	save_reg	
.align 2
int60_vec:
	j	save_reg
.align 2
int61_vec:
	j  	save_reg
.align 2
int62_vec:
	j	save_reg
.align 2
int63_vec:
	j	save_reg

	.extern intmsg   	
################################
# Exception service routine
################################
norm_debug_service:
	#b norm_debug_service
	jl intmsg  

general_service:
	#b general_service
	jl intmsg  

int_service:
	#b int_service 
	jl intmsg  

	.extern irq_dispatch

##########################################################
#     Save all register and jump to interrup label table
#     After completed service routine, load all register
##########################################################
save_reg:
	subi	SP, E_SIZE
	sw	AT, [SP,E_AT]
	sw	BP, [SP,E_BP]
	sw	LR, [SP,E_LR]
	sw	A0, [SP,E_A0]
	sw	A1, [SP,E_A1]
	sw	A2, [SP,E_A2]
	sw	A3, [SP,E_A3]
	sw	T0, [SP,E_T0]
	sw	T1, [SP,E_T1]
	sw	T2, [SP,E_T2]
	sw	T3, [SP,E_T3]
	sw	S0, [SP,E_S0]
	sw	S1, [SP,E_S1]
	sw	S2, [SP,E_S2]
	sw	S3, [SP,E_S3]
	sw	S4, [SP,E_S4]
	sw	S5, [SP,E_S5]
	sw	S6, [SP,E_S6]
	sw	S7, [SP,E_S7]
	sw	S8, [SP,E_S8]
	sw	S9, [SP,E_S9]
	sw	T4, [SP,E_T4]
	sw	T5, [SP,E_T5]
	sw	T6, [SP,E_T6]
	sw	T7, [SP,E_T7]
	sw	T8, [SP,E_T8]
	sw	T9, [SP,E_T9]
	sw	R28,[SP,E_R28]
	sw	JP, [SP,E_JP]
	sw	K0, [SP,E_K0]
	sw	K1, [SP,E_K1]
	mfcr    S1, CP0_COND
	mfcr    S3, CP0_EPC
	sw	S1, [SP,E_CP0_COND]
	sw	S3, [SP,E_CP0_EPC]
	
	mfcr    A0, CP0_CAUSE
	jl	irq_dispatch
 
	lw	AT, [SP,E_AT]
	lw	BP, [SP,E_BP]
	lw	LR, [SP,E_LR]
	lw	A0, [SP,E_A0]
	lw	A1, [SP,E_A1]
	lw	A2, [SP,E_A2]
	lw	A3, [SP,E_A3]
	lw	T0, [SP,E_T0]
	lw	T1, [SP,E_T1]
	lw	T2, [SP,E_T2]
	lw	T3, [SP,E_T3]
	lw	S0, [SP,E_S0]
	lw	S1, [SP,E_S1]
	lw	S2, [SP,E_S2]
	lw	S3, [SP,E_S3]
	lw	S4, [SP,E_S4]
	lw	S5, [SP,E_S5]
	lw	S6, [SP,E_S6]
	lw	S7, [SP,E_S7]
	lw	S8, [SP,E_S8]
	lw	S9, [SP,E_S9]
	lw	T4, [SP,E_T4]
	lw	T5, [SP,E_T5]
	lw	T6, [SP,E_T6]
	lw	T7, [SP,E_T7]
	lw	T8, [SP,E_T8]
	lw	T9, [SP,E_T9]
	lw	R28,[SP,E_R28]
	lw	JP, [SP,E_JP]
	lw	K0, [SP,E_K0]
	lw	K1, [SP,E_K1]
	lw	K0, [SP,E_CP0_COND]
	lw	K1, [SP,E_CP0_EPC]
	mtcr    K0, CP0_COND
	mtcr    K1, CP0_EPC
	addi	SP, E_SIZE
	rte

.text
.global invalid_cache
invalid_cache:
	cache 0x18, [A0,0]
	br LR