📄 sys_register.h
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#define P_BLNDMA_D_BG (UV32*)(BLNDMABASE + 0x00000058)
/**
* SPI: 0x0811_0000 ~ 0x0811_FFFF
*/
#define SPIBASE 0x88110000
#define P_SPI_CTRL (UV32*)(SPIBASE + 0x00000000)
#define P_SPI_TXSTS (UV32*)(SPIBASE + 0x00000004)
#define P_SPI_TXDATA (UV32*)(SPIBASE + 0x00000008)
#define P_SPI_RXSTS (UV32*)(SPIBASE + 0x0000000c)
#define P_SPI_RXDATA (UV32*)(SPIBASE + 0x00000010)
#define P_SPI_MISC (UV32*)(SPIBASE + 0x00000014)
/**
* SIO: 0x0812_0000 ~ 0x0812_FFFF
*/
#define SIOBASE 0x88120000
#define P_SIO_Control (UV32*)(SIOBASE + 0x00000000)
#define P_SIO_AutoTx (UV32*)(SIOBASE + 0x00000004)
#define P_SIO_Addr (UV32*)(SIOBASE + 0x00000008)
#define P_SIO_DATA (UV32*)(SIOBASE + 0x0000000C)
/**
* I2C: 0x0813_0000 ~ 0x0813_FFFF
*/
#define I2CBASE 0x88130000
#define P_I2C_CR (UV32*)(I2CBASE + 0x00000020)
#define P_I2C_INTR (UV32*)(I2CBASE + 0x00000024)
#define P_I2C_CVR (UV32*)(I2CBASE + 0x00000028)
#define P_I2C_ID (UV32*)(I2CBASE + 0x0000002C)
#define P_I2C_ADDR (UV32*)(I2CBASE + 0x00000030)
#define P_I2C_WDATA (UV32*)(I2CBASE + 0x00000034)
#define P_I2C_RDATA (UV32*)(I2CBASE + 0x00000038)
#define P_I2C_PR (UV32*)(I2CBASE + 0x0000003C)
/**
* I2S: 0x0814_0000 ~ 0x0814_FFFF
*/
#define I2SBASE 0x88140000
#define P_I2S_CR (UV32*)(I2SBASE + 0x00000000)
#define P_I2S_MASTER_SETUP (UV32*)(I2SBASE + 0x00000004)
#define P_I2S_IRQ_STS (U32*)(I2SBASE + 0x00000008)
#define P_I2S_FIFO (UV32*)(I2SBASE + 0x0000000C)
#define P_I2S_RDATA (UV32*)(I2SBASE + 0x00000010)
/**
* UART: 0x0815_0000 ~ 0x0815_FFFF
*/
#define UARTBASE 0x88150000
#define P_UART_Data (UV32*)(UARTBASE + 0x00000000)
#define P_UART_ERR (UV32*)(UARTBASE + 0x00000004)
#define P_UART_Ctrl (UV32*)(UARTBASE + 0x00000008)
#define P_UART_BaudRate (UV32*)(UARTBASE + 0x0000000C)
#define P_UART_Status (UV32*)(UARTBASE + 0x00000010)
/**
* TIMER1: 0x0816_0000 ~ 0x0816_0FFF
*/
#define TM0BASE 0x88160000
#define P_TM0_CTRL (UV32*)(TM0BASE + 0x00000000)
#define P_TM0_CCP_CTRL (UV32*)(TM0BASE + 0x00000004)
#define P_TM0_PRELOAD (UV32*)(TM0BASE + 0x00000008)
#define P_TM0_CCP_REG (UV32*)(TM0BASE + 0x0000000c)
#define P_TM0_UPCNT (UV32*)(TM0BASE + 0x00000010)
/**
* TIMER2: 0x0816_1000 ~ 0x0816_1FFF
*/
#define TM1BASE 0x88161000
#define P_TM1_CTRL (UV32*)(TM1BASE + 0x00000000)
#define P_TM1_CCP_CTRL (UV32*)(TM1BASE + 0x00000004)
#define P_TM1_PRELOAD (UV32*)(TM1BASE + 0x00000008)
#define P_TM1_CCP_REG (UV32*)(TM1BASE + 0x0000000c)
#define P_TM1_UPCNT (UV32*)(TM1BASE + 0x00000010)
/**
* TIMER3: 0x0816_2000 ~ 0x0816_2FFF
*/
#define TM2BASE 0x88162000
#define P_TM2_CTRL (UV32*)(TM2BASE + 0x00000000)
#define P_TM2_CCP_CTRL (UV32*)(TM2BASE + 0x00000004)
#define P_TM2_PRELOAD (UV32*)(TM2BASE + 0x00000008)
#define P_TM2_CCP_REG (UV32*)(TM2BASE + 0x0000000c)
#define P_TM2_UPCNT (UV32*)(TM2BASE + 0x00000010)
/**
* TIMER4: 0x0816_3000 ~ 0x0816_3FFF
*/
#define TM3BASE 0x88163000
#define P_TM3_CTRL (UV32*)(TM3BASE + 0x00000000)
#define P_TM3_CCP_CTRL (UV32*)(TM3BASE + 0x00000004)
#define P_TM3_PRELOAD (UV32*)(TM3BASE + 0x00000008)
#define P_TM3_CCP_REG (UV32*)(TM3BASE + 0x0000000c)
#define P_TM3_UPCNT (UV32*)(TM3BASE + 0x00000010)
/**
* TIMER5: 0x0816_4000 ~ 0x0816_4FFF
*/
#define TM4BASE 0x88164000
#define P_TM4_CTRL (UV32*)(TM4BASE + 0x00000000)
#define P_TM4_CCP_CTRL (UV32*)(TM4BASE + 0x00000004)
#define P_TM4_PRELOAD (UV32*)(TM4BASE + 0x00000008)
#define P_TM4_CCP_REG (UV32*)(TM4BASE + 0x0000000c)
#define P_TM4_UPCNT (UV32*)(TM4BASE + 0x00000010)
/**
* TIMER6: 0x0816_5000 ~ 0x0816_5FFF
*/
#define TM5BASE 0x88165000
#define P_TM5_CTRL (UV32*)(TM5BASE + 0x00000000)
#define P_TM5_CCP_CTRL (UV32*)(TM5BASE + 0x00000004)
#define P_TM5_PRELOAD (UV32*)(TM5BASE + 0x00000008)
#define P_TM5_CCP_REG (UV32*)(TM5BASE + 0x0000000c)
#define P_TM5_UPCNT (UV32*)(TM5BASE + 0x00000010)
/**
* RTC: 0x0816_6000 ~ 0x0816_6FFF
*/
#define RTCBASE 0x88166000
#define P_RTC_SEC (UV32*)(RTCBASE + 0x00000000)
#define P_RTC_MIN (UV32*)(RTCBASE + 0x00000004)
#define P_RTC_HOUR (UV32*)(RTCBASE + 0x00000008)
#define P_ALM_SEC (UV32*)(RTCBASE + 0x0000000c)
#define P_ALM_MIN (UV32*)(RTCBASE + 0x00000010)
#define P_ALM_HOUR (UV32*)(RTCBASE + 0x00000014)
#define P_RTC_CTRL (UV32*)(RTCBASE + 0x00000018)
#define P_RTC_STATUS (UV32*)(RTCBASE + 0x0000001c)
#define P_TMB_CTRL (UV32*)(RTCBASE + 0x00000020)
#define P_TMB_STATUS (UV32*)(RTCBASE + 0x00000024)
#define P_RTC_RESET (UV32*)(RTCBASE + 0x00000028)
/**
* WDOG: 0x0817_0000 ~ 0x0817_FFFF
*/
#define WDGBASE 0x88170000
#define P_WDOG_CTRL (UV32*)(WDGBASE + 0x00000000)
#define P_WDOG_CYCLE (UV32*)(WDGBASE + 0x00000004)
#define P_WDOG_CLEAR (UV32*)(WDGBASE + 0x00000008)
/**
* SD: 0x0818_0000 ~ 0x0818_FFFF
*/
#define SDCBASE 0x88180000
#define P_SDC_DataTx (UV32*)(SDCBASE + 0x00000000)
#define P_SDC_DataRx (UV32*)(SDCBASE + 0x00000004)
#define P_SDC_Command (UV32*)(SDCBASE + 0x00000008)
#define P_SDC_Arg (UV32*)(SDCBASE + 0x0000000C)
#define P_SDC_Resp (UV32*)(SDCBASE + 0x00000010)
#define P_SDC_Status (UV32*)(SDCBASE + 0x00000014)
#define P_SDC_Control (UV32*)(SDCBASE + 0x00000018)
#define P_SDC_IntEn (UV32*)(SDCBASE + 0x0000001C)
/**
* FLASH: 0x0819_0000 ~ 0x0819_FFFF
*/
#define FLCBASE 0x88190000
#define P_FL_CR (UV32*)(FLCBASE + 0x00000000)
#define P_FL_CLE (UV32*)(FLCBASE + 0x00000004)
#define P_FL_ALE (UV32*)(FLCBASE + 0x00000008)
#define P_FL_WD (UV32*)(FLCBASE + 0x0000000C)
#define P_FL_RD (UV32*)(FLCBASE + 0x00000010)
#define P_FL_INTEN (UV32*)(FLCBASE + 0x00000014)
#define P_FL_INTSTS (UV32*)(FLCBASE + 0x00000018)
#define P_FL_TRUELP (UV32*)(FLCBASE + 0x0000001C)
#define P_FL_TRUECP (UV32*)(FLCBASE + 0x00000020)
#define P_FL_CALLP (UV32*)(FLCBASE + 0x00000024)
#define P_FL_CALCP (UV32*)(FLCBASE + 0x00000028)
#define P_FL_ECCSTS (UV32*)(FLCBASE + 0x0000002C)
#define P_FL_CALECC (UV32*)(FLCBASE + 0x00000030)
/**
* ADC: 0x081A_0000 ~ 0x081A_FFFF
*/
#define ADCBASE 0x881a0000
#define P_ADC_SETUP (UV32*)(ADCBASE + 0x00000000)
#define P_MIC_GAIN (UV32*)(ADCBASE + 0x00000004)
#define P_ADC_CLOCK_SET (UV32*)(ADCBASE + 0x00000008)
#define P_ADC_SHOLD_SETUP (UV32*)(ADCBASE + 0x0000000c)
#define P_ADC_MIC_CTRL (UV32*)(ADCBASE + 0x00000010)
#define P_ADC_MIC_CTRL2 (UV32*)(ADCBASE + 0x00000014)
#define P_ADC_RData (UV32*)(ADCBASE + 0x00000018)
#define P_ASP_RData (UV32*)(ADCBASE + 0x0000001c)
#define P_MIC_RData (UV32*)(ADCBASE + 0x00000020)
/**
* USB device: 0x081B_0000 ~ 0x081B_FFFF
*/
#define USBDEVBASE 0x881B0000
#define P_USBD_Config (UV32*)(USBDEVBASE+0x000000C0)
#define P_USBD_Device (UV32*)(USBDEVBASE+0x0000015C)
#define P_USBD_Function (UV32*)(USBDEVBASE+0x000000C4)
#define P_USBD_DMAINT (UV32*)(USBDEVBASE+0x00000164)
#define P_USBD_PMR (UV32*)(USBDEVBASE+0x000000C8)
#define P_USBD_EP0Data (UV32*)(USBDEVBASE+0x000000CC)
#define P_USBD_BIData (UV32*)(USBDEVBASE+0x000000D0)
#define P_USBD_BOData (UV32*)(USBDEVBASE+0x000000D4)
#define P_USBD_INTINData (UV32*)(USBDEVBASE+0x000000D8)
#define P_USBD_NullPkt (UV32*)(USBDEVBASE+0x00000160)
#define P_USBD_EPEvent (UV32*)(USBDEVBASE+0x000000DC)
#define P_USBD_GLOINT (UV32*)(USBDEVBASE+0x000000E0)
#define P_USBD_INTEN (UV32*)(USBDEVBASE+0x000000E4)
#define P_USBD_INT (UV32*)(USBDEVBASE+0x000000E8)
#define P_USBD_SCINTEN (UV32*)(USBDEVBASE+0x000000EC)
#define P_USBD_SCINT (UV32*)(USBDEVBASE+0x000000F0)
#define P_USBD_EPAutoSet (UV32*)(USBDEVBASE+0x000000F4)
#define P_USBD_EPSetStall (UV32*)(USBDEVBASE+0x000000F8)
#define P_USBD_EPBufClear (UV32*)(USBDEVBASE+0x000000FC)
#define P_USBD_EPEvntClear (UV32*)(USBDEVBASE+0x00000100)
#define P_USBD_EP0WrtCount (UV32*)(USBDEVBASE+0x00000104)
#define P_USBD_BOWrtCount (UV32*)(USBDEVBASE+0x00000108)
#define P_USBD_EP0BufPointer (UV32*)(USBDEVBASE+0x0000010C)
#define P_USBD_BIBufPointer (UV32*)(USBDEVBASE+0x00000110)
#define P_USBD_BOBufPointer (UV32*)(USBDEVBASE+0x00000114)
#define P_USBD_EP0RTR (UV32*)(USBDEVBASE+0x00000118)
#define P_USBD_EP0RR (UV32*)(USBDEVBASE+0x0000011C)
#define P_USBD_EP0VR (UV32*)(USBDEVBASE+0x00000120)
#define P_USBD_EP0IR (UV32*)(USBDEVBASE+0x00000124)
#define P_USBD_EP0LR (UV32*)(USBDEVBASE+0x00000128)
#define P_USBD_DMAWrtCount (UV32*)(USBDEVBASE+0x00000140)
#define P_USBD_DMAACKCount (UV32*)(USBDEVBASE+0x00000144)
#define P_USBD_EPStall (UV32*)(USBDEVBASE+0x00000150)
#define P_USBD_TNSP (UV32*)(USBDEVBASE+0x0000017C)
/**
* USB host: 0x081C_0000 ~ 0x081C_FFFF
*/
#define USBHOSTBASE 0x881C0000
#define P_USBH_Config (UV32*)(USBHOSTBASE+0x00000000)
#define P_USBH_TimeConfig (UV32*)(USBHOSTBASE+0x00000004)
#define P_USBH_Data (UV32*)(USBHOSTBASE+0x00000008)
#define P_USBH_Transfer (UV32*)(USBHOSTBASE+0x0000000C)
#define P_USBH_DveAddr (UV32*)(USBHOSTBASE+0x00000010)
#define P_USBH_DveEp (UV32*)(USBHOSTBASE+0x00000014)
#define P_USBH_TXCount (UV32*)(USBHOSTBASE+0x00000018)
#define P_USBH_RXCount (UV32*)(USBHOSTBASE+0x0000001C)
#define P_USBH_FIFOInPointer (UV32*)(USBHOSTBASE+0x00000020)
#define P_USBH_FIFOOutPointer (UV32*)(USBHOSTBASE+0x00000024)
#define P_USBH_AutoInByteCount (UV32*)(USBHOSTBASE+0x00000028)
#define P_USBH_AutoOutByteCount (UV32*)(USBHOSTBASE+0x0000002C)
#define P_USBH_AutoTrans (UV32*)(USBHOSTBASE+0x00000030)
#define P_USBH_Status (UV32*)(USBHOSTBASE+0x00000034)
#define P_USBH_INT (UV32*)(USBHOSTBASE+0x00000038)
#define P_USBH_INTEN (UV32*)(USBHOSTBASE+0x0000003C)
#define P_USBH_StorageRST (UV32*)(USBHOSTBASE+0x00000040)
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