📄 sys_register.h
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/******************************************************************************
*
* The information contained herein is the exclusive property of
* Sunplus Technology Co. And shall not be distributed, reproduced,
* or disclosed in whole in part without prior written permission.
*
* (C) COPYRIGHT 2005 SUNPLUS TECHNOLOGY CO.
* ALL RIGHTS RESERVED
*
* The entire notice above must be reproduced on all authorized copies.
*
*****************************************************************************/
/******************************************************************************
* Filename: Sys_Register.h
* Author: Robin.xjliu (eMail: xjliu@sunplus.com)
* Tel: 00885-028-87848688-5884
* Date: 2005-11-03
* Description: all the SPG290 Register define
* Reference:
* Version history:
*-----------------------------------------------------------------------------
* Version YYYY-MM-DD-INDEX Modified By Description
* 1.0.0 2005-11-03 xjliu Create
* 1.0.1 2006-03-08 xjliu add volatile define register port
*
*****************************************************************************/
#ifndef _SYS_REGISTER_H
#define _SYS_REGISTER_H
#include "Sys_Define.h"
#ifndef SCOREIDE_SPG290_H_11538_14771__INCLUDED_
#define SCOREIDE_SPG290_H_11538_14771__INCLUDED_
#define VOLATILE
#define _WritePort(Port,Value) {*((UV32*)(Port)) = (UV32)(Value);}
#define _ReadPort(Port) (*((UV32*)(Port)))
/**
* general register define
*/
typedef union
{
U32 DW;
struct
{
U32 bit0 : 1;
U32 bit1 : 1;
U32 bit2 : 1;
U32 bit3 : 1;
U32 bit4 : 1;
U32 bit5 : 1;
U32 bit6 : 1;
U32 bit7 : 1;
U32 bit8 : 1;
U32 bit9 : 1;
U32 bit10 : 1;
U32 bit11 : 1;
U32 bit12 : 1;
U32 bit13 : 1;
U32 bit14 : 1;
U32 bit15 : 1;
U32 ReservedH :16;
} B;
}GEN_REG_DEF;
/**
* P_SP_Control(0x88010004) register define
*/
typedef union
{
U32 DW;
struct
{
U32 Sp_en : 1;
U32 Coord_sel : 1;
U32 Reserved :14;
U32 ReservedH :16;
} B;
}P_Sp_Control_DEF;
/**
* CSI: 0x0800_0000 ~ 0x0800_FFFF
*/
#define CSIBASE 0x88000000
#define P_CSI_TG_CR (UV32*)(CSIBASE + 0x00000000)
#define P_CSI_TG_LSTART (UV32*)(CSIBASE + 0x00000004)
#define P_CSI_TG_START (UV32*)(CSIBASE + 0x00000008)
#define P_CSI_TG_END (UV32*)(CSIBASE + 0x0000000C)
#define P_CSI_TG_BLACK (UV32*)(CSIBASE + 0x00000010)
#define P_CSI_TG_BSUPPER (UV32*)(CSIBASE + 0x00000014)
#define P_CSI_TG_BSLOWER (UV32*)(CSIBASE + 0x00000018)
#define P_CSI_TG_TRANSP (UV32*)(CSIBASE + 0x0000001C)
#define P_CSI_TG_FBSADDR0 (UV32*)(CSIBASE + 0x00000020)
#define P_CSI_TG_FBSADDR1 (UV32*)(CSIBASE + 0x00000024)
#define P_CSI_TG_FBSADDR2 (UV32*)(CSIBASE + 0x00000028)
#define P_CSI_TG_CAP (UV32*)(CSIBASE + 0x0000002C)
#define P_CSI_MD_CR (UV32*)(CSIBASE + 0x00000030)
#define P_CSI_MD_SADDR (UV32*)(CSIBASE + 0x00000034)
#define P_CSI_MD_POS (UV32*)(CSIBASE + 0x00000038)
#define P_CSI_MD_SADDR1 (UV32*)(CSIBASE + 0x0000003C)
#define P_CSI_MD_CTABLE0 (UV32*)(CSIBASE + 0x00000040)
#define P_CSI_MD_CTABLE1 (UV32*)(CSIBASE + 0x00000044)
#define P_CSI_MD_CTABLE2 (UV32*)(CSIBASE + 0x00000048)
#define P_CSI_MD_CTABLE3 (UV32*)(CSIBASE + 0x0000004C)
#define P_CSI_MD_REG1 (UV32*)(CSIBASE + 0x00000050)
#define P_CSI_MD_REG2 (UV32*)(CSIBASE + 0x00000054)
#define P_CSI_MD_REG3 (UV32*)(CSIBASE + 0x00000058)
#define P_CSI_MD_TH (UV32*)(CSIBASE + 0x0000005C)
// #define P_CSI_MD_YUV (UV32*)(CSIBASE + 0x00000070)
#define P_CSI_MD_RGB (UV32*)(CSIBASE + 0x00000074)
#define P_CSI_IRQEN (UV32*)(CSIBASE + 0x00000078)
#define P_CSI_IRQSTS (UV32*)(CSIBASE + 0x0000007C)
#define P_CSI_Y2R_A1 (UV32*)(CSIBASE + 0x000000E8)
#define P_CSI_Y2R_A2 (UV32*)(CSIBASE + 0x000000EC)
#define P_CSI_Y2R_A3 (UV32*)(CSIBASE + 0x000000F0)
#define P_CSI_R2Y_A1 (UV32*)(CSIBASE + 0x000000F4)
#define P_CSI_R2Y_A2 (UV32*)(CSIBASE + 0x000000F8)
#define P_CSI_R2Y_A3 (UV32*)(CSIBASE + 0x000000FC)
/**
* PPU: 0x0801_0000 ~ 0x0801_FFFF
*/
#define PPUBASE 0x88010000
#define P_PPU_CONTROL (UV32*)(PPUBASE + 0x00000000)
#define P_SP_Control ((volatile P_Sp_Control_DEF *) (PPUBASE + 0x00000004))
#define P_SP_MAX (UV32*)(PPUBASE + 0x00000008)
#define P_BLN_FORMULA (UV32*)(PPUBASE + 0x0000000C)
#define P_TRANS_RGB (UV32*)(PPUBASE + 0x00000010)
#define P_PPU_TX1_X (UV32*)(PPUBASE + 0x00000020)
#define P_PPU_TX1_Y (UV32*)(PPUBASE + 0x00000024)
#define P_PPU_TX1_Attribute (UV32*)(PPUBASE + 0x00000028)
#define P_PPU_TX1_Control (UV32*)(PPUBASE + 0x0000002C)
#define P_PPU_TX1_N_PTR (UV32*)(PPUBASE + 0x00000030)
#define P_PPU_TX1_Blending (UV32*)(PPUBASE + 0x00000038)
#define P_PPU_TX2_X (UV32*)(PPUBASE + 0x0000003C)
#define P_PPU_TX2_Y (UV32*)(PPUBASE + 0x00000040)
#define P_PPU_TX2_Attribute (UV32*)(PPUBASE + 0x00000044)
#define P_PPU_TX2_Control (UV32*)(PPUBASE + 0x00000048)
#define P_PPU_TX2_N_PTR (UV32*)(PPUBASE + 0x0000004C)
#define P_PPU_TX2_Blending (UV32*)(PPUBASE + 0x00000054)
#define P_PPU_TX3_X (UV32*)(PPUBASE + 0x00000058)
#define P_PPU_TX3_Y (UV32*)(PPUBASE + 0x0000005C)
#define P_PPU_TX3_Attribute (UV32*)(PPUBASE + 0x00000060)
#define P_PPU_TX3_Control (UV32*)(PPUBASE + 0x00000064)
#define P_PPU_TX3_N_PTR (UV32*)(PPUBASE + 0x00000068)
#define P_PPU_TX3_Blending (UV32*)(PPUBASE + 0x00000070)
#define P_PPU_VComp_Value (UV32*)(PPUBASE + 0x00000074)
#define P_PPU_VComp_Offset (UV32*)(PPUBASE + 0x00000078)
#define P_PPU_VComp_Step (UV32*)(PPUBASE + 0x0000007C)
#define P_IRQ_CONTROL (UV32*)(PPUBASE + 0x00000080)
#define P_IRQ_STATUS (UV32*)(PPUBASE + 0x00000084)
#define P_IRQ_TMV (UV32*)(PPUBASE + 0x00000088)
#define P_IRQ_TMH (UV32*)(PPUBASE + 0x0000008C)
#define P_VBLK_TIME (UV32*)(PPUBASE + 0x00000090)
// #define P_LINE_COUNTER (UV32*)(PPUBASE + 0x00000094)
#define P_PPU_TX1_SA1 (UV32*)(PPUBASE + 0x000000A0)
#define P_PPU_TX1_SA2 (UV32*)(PPUBASE + 0x000000A4)
#define P_PPU_TX1_SA3 (UV32*)(PPUBASE + 0x000000A8)
#define P_PPU_TX2_SA1 (UV32*)(PPUBASE + 0x000000AC)
#define P_PPU_TX2_SA2 (UV32*)(PPUBASE + 0x000000B0)
#define P_PPU_TX2_SA3 (UV32*)(PPUBASE + 0x000000B4)
#define P_PPU_TX3_SA1 (UV32*)(PPUBASE + 0x000000B8)
#define P_PPU_TX3_SA2 (UV32*)(PPUBASE + 0x000000BC)
#define P_PPU_TX3_SA3 (UV32*)(PPUBASE + 0x000000C0)
#define P_PPU_FB_SA1 (UV32*)(PPUBASE + 0x000000C4)
#define P_PPU_FB_SA2 (UV32*)(PPUBASE + 0x000000C8)
#define P_PPU_FB_SA3 (UV32*)(PPUBASE + 0x000000CC)
#define P_SP_BUF_SA ((volatile GEN_REG_DEF *) (PPUBASE + 0x000000D0))
#define P_BG_COLOR_PALETTE (UV32*)(PPUBASE + 0x00001000)
#define P_SP_COLOR_PALETTE (UV32*)(PPUBASE + 0x00001800)
#define P_PPU_Tx_HOffset (UV32*)(PPUBASE + 0x00002000)
#define P_PPU_Tx1_HCmp (UV32*)(PPUBASE + 0x00003000)
#define P_PPU_Sprite (UV32*)(PPUBASE + 0x00004000)
/**
* TV: 0x0803_0000 ~ 0x0803_FFFF
*/
#define TVEBASE 0x88030000
#define P_TV_CONTROL (UV32*)(TVEBASE + 0x00000000)
#define P_TV_Saturation (UV32*)(TVEBASE + 0x00000004)
#define P_TV_Hue (UV32*)(TVEBASE + 0x00000008)
#define P_TV_FADE (UV32*)(TVEBASE + 0x0000000C)
#define P_TV_LP_FILTER_SEL (UV32*)(TVEBASE + 0x00000010)
// #define P_TV_ACT_END (UV32*)(TVEBASE + 0x00000014)
// #define P_TV_IRQTMV (UV32*)(TVEBASE + 0x00000018)
// #define P_TV_IRQTMH (UV32*)(TVEBASE + 0x0000001C)
#define P_TV_LINECON (UV32*)(TVEBASE + 0x00000020)
#define P_LIGHTGUN_CTL (UV32*)(TVEBASE + 0x0000002C)
#define P_LIGHTGUN0_X (UV32*)(TVEBASE + 0x00000030)
#define P_LIGHTGUN0_Y (UV32*)(TVEBASE + 0x00000034)
#define P_LIGHTGUN1_X (UV32*)(TVEBASE + 0x00000038)
#define P_LIGHTGUN1_Y (UV32*)(TVEBASE + 0x0000003C)
/**
* LCD: 0x0804_0000 ~ 0x0804_FFFF
*/
#define TFTBASE 0x88040000
#define P_TFT_CTRL (UV32*)(TFTBASE + 0x00000000)
#define P_DATA_FMT (UV32*)(TFTBASE + 0x00000004)
#define P_HOR_ACT (UV32*)(TFTBASE + 0x00000008)
#define P_HOR_FBLK (UV32*)(TFTBASE + 0x0000000C)
#define P_HOR_BBLK (UV32*)(TFTBASE + 0x00000010)
#define P_HOR_SYNCW (UV32*)(TFTBASE + 0x00000014)
#define P_VER_ACT (UV32*)(TFTBASE + 0x00000018)
#define P_VER_FBLK (UV32*)(TFTBASE + 0x0000001C)
#define P_VER_BBLK (UV32*)(TFTBASE + 0x00000020)
#define P_VER_SYNCW (UV32*)(TFTBASE + 0x00000024)
#define P_FB_ATTRIB (UV32*)(TFTBASE + 0x00000028)
#define P_STR_LNO (UV32*)(TFTBASE + 0x0000002C)
#define P_STR_PNO (UV32*)(TFTBASE + 0x00000030)
#define P_PIX_NUM (UV32*)(TFTBASE + 0x00000034)
#define P_DUMP_PIX (UV32*)(TFTBASE + 0x00000038)
#define P_TFT_ST (UV32*)(TFTBASE + 0x0000003C)
#define P_DATA_SEQ (UV32*)(TFTBASE + 0x00000040)
#define P_TFT_INT (UV32*)(TFTBASE + 0x00000050)
#define P_TFT_DM (UV32*)(TFTBASE + 0x000000A0)
// CSTN
#define P_STN_CTRL (UV32*)(TFTBASE + 0x00001000)
#define P_LCDCLK (UV32*)(TFTBASE + 0x00001004)
#define P_STN_SEG_NUM (UV32*)(TFTBASE + 0x00001008)
#define P_STN_COM_NUM (UV32*)(TFTBASE + 0x0000100C)
#define P_STN_STR_LNO (UV32*)(TFTBASE + 0x00001010)
#define P_STN_STR_PNO (UV32*)(TFTBASE + 0x00001014)
#define P_STN_DMY_PIX (UV32*)(TFTBASE + 0x00001018)
#define P_STN_LT (UV32*)(TFTBASE + 0x0000101C)
#define P_STN_FM (UV32*)(TFTBASE + 0x00001020)
#define P_STN_BUF_CTRL (UV32*)(TFTBASE + 0x00001024)
#define P_STN_ATTR (UV32*)(TFTBASE + 0x00001028)
#define P_STN_MSC (UV32*)(TFTBASE + 0x0000102C)
#define P_STN_DM (UV32*)(TFTBASE + 0x000010A0)
/**
* SPU: 0x0805_0000 ~ 0x0805_FFFF
*/
#define SPUBASE 0x88050000
//****************************************
// SPU Control Register *
//****************************************
//Used as pointer only.
#define P_SPU_ChEnL ((UV32 *)(0x88051000)) //Channel Enable
#define P_SPU_Vol ((UV32 *)(0x88051004)) //Main Volume
#define P_SPU_ChFiqEnL ((UV32 *)(0x88051008)) //Channel FIQ Enable
#define P_SPU_ChFiqStsL ((UV32 *)(0x8805100C)) //Channel FIQ Status
#define P_SPU_BeatBaseCnt ((UV32 *)(0x88051010)) //Beat Base Count
#define P_SPU_BeatCnt ((UV32 *)(0x88051014)) //Beat Counter
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