specctra.did

candence工程文件

define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA6 (add_group '_XPP_T.1_U7-61'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED4)
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED4 (add_group '_XPP_T.1_U8-38'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED4 (add_group '_XPP_T.1_U7-8'))
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA7)
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA7 (add_group '_XPP_T.1_U8-20'))
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA7 (add_group '_XPP_T.1_U7-62'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED5)
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED5 (add_group '_XPP_T.1_U8-40'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED5 (add_group '_XPP_T.1_U7-10'))
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA8)
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA8 (add_group '_XPP_T.1_U8-19'))
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA8 (add_group '_XPP_T.1_U7-63'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED6)
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED6 (add_group '_XPP_T.1_U8-42'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED6 (add_group '_XPP_T.1_U7-11'))
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA9)
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA9 (add_group '_XPP_T.1_U8-18'))
define (group_set _REL_DELAY_ADDR_BUS_M1_R_EA9 (add_group '_XPP_T.1_U7-64'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED7)
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED7 (add_group '_XPP_T.1_U8-44'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED7 (add_group '_XPP_T.1_U7-13'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED8)
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED8 (add_group '_XPP_T.1_U8-30'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED8 (add_group '_XPP_T.1_U7-74'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED9)
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED9 (add_group '_XPP_T.1_U8-32'))
define (group_set _REL_DELAY_DATA_BUS_M2_R_ED9 (add_group '_XPP_T.1_U7-76'))
define (region cct_misc_95571716_0 (polygon TOP 0 -1540 140 -1540 -940 -460 -940 -460 140 -1540 140 ))
define (region cct_misc_95571716_3 (polygon BOTTOM 0 -1540 140 -1540 -940 -460 -940 -460 140 -1540 140 ))
rule PCB (width 8)
rule PCB (clearance 8 (type wire_wire))
rule PCB (clearance 8 (type wire_smd))
rule PCB (clearance 8 (type wire_pin))
rule PCB (clearance 8 (type wire_via))
rule PCB (clearance 6 (type smd_smd))
rule PCB (clearance 6 (type smd_pin))
rule PCB (clearance 8 (type smd_via))
rule PCB (clearance 6 (type pin_pin))
rule PCB (clearance 8 (type pin_via))
rule PCB (clearance 8 (type via_via))
rule PCB (clearance 8 (type test_test))
rule PCB (clearance 8 (type test_wire))
rule PCB (clearance 8 (type test_smd))
rule PCB (clearance 8 (type test_pin))
rule PCB (clearance 8 (type test_via))
rule PCB (clearance 5 (type buried_via_gap))
rule PCB (clearance 0 (type area_wire))
rule PCB (clearance 0 (type area_smd))
rule PCB (clearance 0 (type area_area))
rule PCB (clearance 0 (type area_pin))
rule PCB (clearance 0 (type area_via))
rule PCB (clearance 0 (type area_test))
rule class CLK_SPACE (clearance 12 (type wire_wire))
rule class CLK_SPACE (clearance 12 (type wire_via))
rule class CLK_SPACE (clearance 12 (type smd_via))
rule class CLK_SPACE (clearance 12 (type pin_via))
rule class CLK_SPACE (clearance 12 (type via_via))
rule class CLK_SPACE (clearance 12 (type test_test))
rule class CLK_SPACE (clearance 12 (type test_wire))
rule class CLK_SPACE (clearance 12 (type test_smd))
rule class CLK_SPACE (clearance 12 (type test_pin))
rule class CLK_SPACE (clearance 12 (type test_via))
rule class CLK_PHY (width 12)
rule region cct_misc_95571716_0 (width 8)
rule region cct_misc_95571716_0 (clearance 8 (type wire_wire))
rule region cct_misc_95571716_0 (clearance 8 (type wire_via))
rule region cct_misc_95571716_0 (clearance 8 (type smd_via))
rule region cct_misc_95571716_0 (clearance 8 (type pin_via))
rule region cct_misc_95571716_0 (clearance 8 (type via_via))
rule region cct_misc_95571716_0 (clearance 8 (type test_test))
rule region cct_misc_95571716_0 (clearance 8 (type test_wire))
rule region cct_misc_95571716_0 (clearance 8 (type test_smd))
rule region cct_misc_95571716_0 (clearance 8 (type test_pin))
rule region cct_misc_95571716_0 (clearance 8 (type test_via))
rule region cct_misc_95571716_3 (width 8)
rule region cct_misc_95571716_3 (clearance 8 (type wire_wire))
rule region cct_misc_95571716_3 (clearance 8 (type wire_via))
rule region cct_misc_95571716_3 (clearance 8 (type smd_via))
rule region cct_misc_95571716_3 (clearance 8 (type pin_via))
rule region cct_misc_95571716_3 (clearance 8 (type via_via))
rule region cct_misc_95571716_3 (clearance 8 (type test_test))
rule region cct_misc_95571716_3 (clearance 8 (type test_wire))
rule region cct_misc_95571716_3 (clearance 8 (type test_smd))
rule region cct_misc_95571716_3 (clearance 8 (type test_pin))
rule region cct_misc_95571716_3 (clearance 8 (type test_via))
rule pcb (tjunction on)(junction_type all)
rule pcb (staggered_via on (min_gap 5)(max_gap -0.001))
rule class CLK_PHY (tjunction on)(junction_type all)
rule class CLK_PHY (staggered_via on (min_gap 5)(max_gap -0.001))
circuit class CLK_PHY (use_via VIA60_35_95 )
rule layer TOP (restricted_layer_length_factor 1)
rule layer BOTTOM (restricted_layer_length_factor 1)
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA10 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA11 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA12 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED10 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA13 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED11 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA14 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED12 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED13 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED14 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED15 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M1 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M2 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA2 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED0 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA3 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED1 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA4 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED2 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA5 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED3 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA6 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED4 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA7 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED5 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA8 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED6 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_ADDR_BUS_M1_R_EA9 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED7 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED8 (match_group_length on (tolerance 100.00000))
circuit group_set _REL_DELAY_DATA_BUS_M2_R_ED9 (match_group_length on (tolerance 100.00000))
circuit group '_XPP_U6-M20_U7-10' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-N18_U7-11' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-N20_U7-74' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-N19_U7-13' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-R20_U7-80' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-P20_U7-77' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-T20_U7-83' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-P18_U7-76' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-T18_U7-82' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-Y10_U7-68' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-T19_U7-85' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-R19_U7-79' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-K18_U7-2' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-P1_U7-51' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-R2_U7-50' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-K19_U7-4' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-P2_U7-53' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-L18_U7-5' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-U1_U7-40' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-N3_U7-56' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-P3_U7-54' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-L19_U7-7' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-V4_U7-31' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-U3_U7-42' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-T1_U7-45' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-M19_U7-8' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-V10_U8-8' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-R3_U7-48' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-W4_U7-33' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-V1_U7-37' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-T2_U7-47' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-V2_U7-36' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-W14_U8-5' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-V14_U8-6' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-Y14_U8-4' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-Y3_U7-34' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-W8_U8-21' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-V8_U8-22' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-U2_U7-39' (max_total_length 6000) (min_total_length 3000)
circuit group '_XPP_U6-W13_U8-7' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-W7_U8-23' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-V7_U8-24' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-Y8_U8-20' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-Y6_U8-25' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-V9_U8-19' (max_total_length 6000) (min_total_length 4000)
circuit group '_XPP_U6-Y9_U8-18' (max_total_length 6000) (min_total_length 4000)
write colormap _notify.std
# do C:/DOCUME~1/YHL/LOCALS~1/Temp/#Taaaaah02848.tmp
unselect all routing
select net R_ED14
set route_diagonal 0
grid wire 1.000000 (direction x) (offset 0.000000)
grid wire 1.000000 (direction y) (offset 0.000000)
grid via 1.000000 (direction x) (offset 0.000000)
grid via 1.000000 (direction y) (offset 0.000000)
protect all wires
direction TOP horizontal
select layer TOP
unprotect layer_wires TOP
direction BOTTOM vertical
select layer BOTTOM
unprotect layer_wires BOTTOM
cost via -1
set turbo_stagger off
limit outside -1
rule pcb (patterns_allowed  trombone accordion)
set pattern_stacking on
rule pcb (sawtooth_amplitude -1 -1)
rule pcb (sawtooth_gap -1)
rule pcb (accordion_amplitude -1 -1)
rule pcb (accordion_gap -1)
rule pcb (trombone_run_length -1)
rule pcb (trombone_gap -1)
unprotect selected
route 25 1
clean 2
write routes (changed_only) (reset_changed) C:/DOCUME~1/YHL/LOCALS~1/Temp/#Taaaaai02848.tmp
# do C:/DOCUME~1/YHL/LOCALS~1/Temp/#Taaaaal02848.tmp
unselect all objects
select net R_ED0
select net R_ED8
select net R_ED15
select net R_ED6
select net R_ED4
select net R_ED5
select net R_ED7
select net R_ED3
select net R_ED2
select net R_ED1
select net R_ED14
select net R_ED9
select net R_ED10
select net +UNUSED_PINS+
select net orphan_net
unfix net orphan_net
unprotect selected
delete selected
unprotect selected polygon
delete selected polygon
unselect all objects
read route C:/DOCUME~1/YHL/LOCALS~1/Temp/#Taaaaak02848.tmp
fix net orphan_net