myproj.opj
来自「candence工程文件」· OPJ 代码 · 共 228 行
OPJ
228 行
(ExpressProject "myproj"
(ProjectVersion "19981106")
(ProjectType "PCB")
(Folder "Design Resources"
(Folder "Library")
(NoModify)
(File ".\myproj.dsn"
(Type "Schematic Design"))
(BuildFileAddedOrDeleted "x")
(CompileFileAddedOrDeleted "x")
(Netlist_TAB "0")
(ANNOTATE_Scope "0")
(ANNOTATE_Mode "1")
(ANNOTATE_Action "1")
(Annotate_Page_Order "0")
(ANNOTATE_Reset_References_to_1 "FALSE")
(ANNOTATE_No_Page_Number_Change "FALSE")
(ANNOTATE_Property_Combine "{Value}{Source Package}{package}")
(ANNOTATE_IncludeNonPrimitive "FALSE")
(ANNOTATE_Refdes_Control_Required "FALSE")
(DRC_Scope "0")
(DRC_Action "0")
(DRC_Create_Warnings "TRUE")
(DRC_Check_Ports "TRUE")
(DRC_Check_Off-Page_Connectors "TRUE")
(DRC_Identical_References "TRUE")
(DRC_Type_Mismatch "TRUE")
(DRC_Report_Ports_and_Off-page_Connectors "TRUE")
(DRC_SDT_Compatibility "FALSE")
(DRC_Report_Off-grid_Objects "TRUE")
(DRC_Check_Unconnected_Nets "TRUE")
(DRC_Check_for_Misleading_TAP "TRUE")
(DRC_Visible_Power_pins "TRUE")
(DRC_Report_Netnames "FALSE")
(DRC_View_Output "TRUE")
(DRC_Report_File
"F:\Cadence15.7于博士\candence工程文件\原理图工程文件\mysch\DRC.DRC")
("Create Allegro Netlist" "TRUE")
("Allegro Netlist Directory" "allegro")
("View Allegro Netlist Files" "FALSE")
("Update Allegro Board" "TRUE")
("Allegro Netlist Output Board File"
"E:\class_cadence\creatboard\dspsystem.brd")
("Allegro Netlist Remove Etch" "FALSE")
("Allegro Netlist Place Changed Component" "ALWAYS_REPLACE")
("Allegro Netlist Open Board in Allegro" "NEITHER")
("Allegro Setup Configuration File"
"C:\Cadence\SPB_15.7\tools\capture\allegro.cfg")
("Allegro Setup Backup Versions" "3")
("Allegro Netlist Combine Property String" "PCB Footprint")
("Allegro Netlist Ignore Fixed Property" "FALSE")
("Allegro Netlist User Defined Property" "TRUE")
(BOM_Scope "0")
(BOM_Mode "0")
(BOM_Report_File "E:\CLASS_CADENCE\MYSCH\MYPROJ.BOM")
(BOM_Merge_Include "FALSE")
(BOM_Property_Combine_7.0 "{Item}\t{Quantity}\t{Reference}\t{Value}")
(BOM_Header "Item\tQuantity\tReference\tPart")
(BOM_Include_File "E:\CLASS_CADENCE\MYSCH\MYPROJ.INC")
(BOM_Include_File_Combine_7.0 "{Item}\t{Quantity}\t{Reference}\t{Value}")
(BOM_One_Part_Per_Line "TRUE")
(Open_BOM_in_Excel "FALSE")
(BOM_View_Output "TRUE")
(Board_sim_option "VHDL_flow")
("Allegro Netlist Input Board File"
"E:\class_cadence\creatboard\dspsystem.brd")
(DRC_Run_Electrical_Rules "TRUE")
(DRC_Run_Physical_Rules "FALSE")
(DRC_Check_Single_Node_Nets "TRUE")
(DRC_Check_No_Driving_Source "TRUE")
(DRC_Check_Duplicate_NetNames "TRUE")
(DRC_Check_Floating_Pins "TRUE")
(DRC_Check_Physical_Power_Pins_Visibility "TRUE")
(DRC_Check_PCB_Footprint_Property "TRUE")
(DRC_Check_Normal_Convert_View_Sync "TRUE")
(DRC_Check_Incorrect_PinGroup_Assignment "TRUE")
(DRC_Check_High_Speed_Props_Syntax "TRUE")
(DRC_Check_Missing_Pin_Numbers "TRUE")
(DRC_Check_Device_With_No_Pins "TRUE")
(DRC_Check_Power_Ground_Short "TRUE")
(DRC_Report_Unused_Part_Packages "TRUE")
(DRC_Check_Name_Prop_For_HierBlocks "TRUE"))
(Folder "Outputs"
(File ".\allegro\pstxnet.dat"
(Type "Report")
(DisplayName "pstxnet.dat"))
(File ".\allegro\pstxprt.dat"
(Type "Report")
(DisplayName "pstxprt.dat"))
(File ".\allegro\pstchip.dat"
(Type "Report")
(DisplayName "pstchip.dat"))
(File ".\myproj.drc"
(Type "Report"))
(File ".\myproj.bom"
(Type "Report"))
(File ".\drc.drc"
(Type "Report")))
(Folder "Referenced Projects")
(PartMRUSelector
(GND
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
(DeviceIndex "0"))
(VCC_BAR
(LibraryName "C:\CADENCE\SPB_15.2\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
(DeviceIndex "0"))
(TP_SS
(FullPartName "TP_SS.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(OFFPAGELEFT-L
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
(DeviceIndex "0"))
(R
(FullPartName "R.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
(DeviceIndex "0"))
("CAP NP"
(FullPartName "CAP NP.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
(DeviceIndex "0"))
(CAPACITOR
(FullPartName "CAPACITOR.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
(DeviceIndex "0"))
("HEADER 6X2"
(FullPartName "HEADER 6X2.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
(DeviceIndex "0"))
("HEADER 5X2"
(FullPartName "HEADER 5X2.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
(DeviceIndex "0"))
(C
(FullPartName "C.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
(DeviceIndex "0"))
("HEADER 7X2"
(FullPartName "HEADER 7X2.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
(DeviceIndex "0"))
(JUMPER7
(FullPartName "JUMPER7.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
(DeviceIndex "0"))
(RS4
(FullPartName "RS4.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(CON4
(FullPartName "CON4.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
(DeviceIndex "0"))
(CON5
(FullPartName "CON5.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CONNECTOR.OLB")
(DeviceIndex "0"))
(FB
(FullPartName "FB.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(CLOCK_DIP8
(FullPartName "CLOCK_DIP8.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(VOT3
(FullPartName "VOT3.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(CY2303
(FullPartName "CY2303.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(OFFPAGELEFT-R
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\CAPSYM.OLB")
(DeviceIndex "0"))
("SW PUSHBUTTON-DPST"
(FullPartName "SW PUSHBUTTON-DPST.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
(DeviceIndex "0"))
(LED
(FullPartName "LED.Normal")
(LibraryName "C:\CADENCE\SPB_15.7\TOOLS\CAPTURE\LIBRARY\DISCRETE.OLB")
(DeviceIndex "0"))
("EMI FILTER"
(FullPartName "EMI FILTER.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(JTAG_14
(FullPartName "JTAG_14.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "0"))
(TMS320C6713GDP
(FullPartName "TMS320C6713GDPDD.Normal")
(LibraryName "E:\CLASS_CADENCE\CAPTURETLIBRARY\MYLIBRARY.OLB")
(DeviceIndex "3")))
(GlobalState
(FileView
(Path "Design Resources")
(Path "Design Resources" ".\myproj.dsn")
(Path "Outputs")
(Select "Design Resources" ".\myproj.dsn"))
(HierarchyView)
(Doc
(Type "COrCapturePMDoc")
(Frame
(Placement "44 0 1 160 737 -4 -30 -5 195 2 635"))
(Tab 0)))
(LastUsedLibraryBrowseDirectory "E:\class_cadence\capturetlibrary")
(Folder "Simulation Resources"
(Folder "Indesign"
(File ".\indesign\cds.lib"
(Type "Report")
(DisplayName ".\Indesign\cds.lib"))
(File ".\indesign\hdl.var"
(Type "Report")
(DisplayName ".\Indesign\hdl.var"))
(File ".\indesign\myproj.vhd"
(Type "VHDL Source")
(DisplayName ".\Indesign\myproj.vhd"))
(File ".\indesign\stubi.vhd"
(Type "VHDL Source")
(DisplayName ".\Indesign\StubI.vhd"))
(File ".\indesign\sdf.cmd"
(Type "Report")
(DisplayName ".\Indesign\sdf.cmd"))))
(ISPCBBASICLICENSE "false"))
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