allegro.jrl

candence工程文件

\t (00:00:03) allegro 15.7 p007 (v15-7-42E) i86
\t (00:00:03) 

\t (00:00:03) Starting new drawing...
\i (00:00:04) trapsize 731
\i (00:00:04) trapsize 857
\i (00:00:04) trapsize 857
\i (00:00:28) tline calculator 
   (00:00:29) Loading tlcalculators.cxt 
\i (00:00:51) setwindow form.tlcalculators
\i (00:00:51) FORM tlcalculators embedded_microstrip  
\i (00:00:55) FORM tlcalculators stripline  
\i (00:00:56) FORM tlcalculators coupled_microstrip  
\i (00:00:58) FORM tlcalculators done  
\i (00:01:03) setwindow pcb
\i (00:01:03) signal library 
   (00:01:04) Loading sigallegro.cxt 
   (00:01:04) Loading signal.cxt 
   (00:01:04) Loading skillExt.cxt 
\i (00:01:07) setwindow form.siglibrary
\i (00:01:07) FORM siglibrary cancel  
\i (00:01:46) setwindow pcb
\i (00:01:46) open 
\i (00:02:10) fillin "E:\WorkCadence\schv2.0\PCB\MYBoard.brd"
\i (00:02:10) cd "E:\WorkCadence\schv2.0\PCB"
\t (00:02:10) Opening existing drawing...
\t (00:02:11) Grids are drawn 16.0, 16.0 apart for enhanced viewability.
\i (00:02:11) trapsize 78
\d (00:02:11) Database opened: E:/WorkCadence/schv2.0/PCB/MYBoard.brd
\i (00:02:21) cdsdoc allegro allegrolaunch 
\t (00:02:24) cdsdoc is starting, please wait...
\i (00:02:55) exit