📄 sys_register.h
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#define P_SPU_EnvClk0 ((UV32 *)(0x88051018)) //Envelope Interval Select
#define P_SPU_EnvClk1 ((UV32 *)(0x8805101C)) //Envelope Interval Select
#define P_SPU_EnvClk2 ((UV32 *)(0x88051020)) //Envelope Interval Select
#define P_SPU_EnvClk3 ((UV32 *)(0x88051024)) //Envelope Interval Select
#define P_SPU_ChEnvRampDownL ((UV32 *)(0x88051028)) //Envelope Fase Ramp Down
#define P_SPU_ChStopStsL ((UV32 *)(0x8805102C)) //Stop Channel Status
#define P_SPU_ChZeroCrossEnL ((UV32 *)(0x88051030)) //Zero Cross Enable
#define P_SPU_Control ((UV32 *)(0x88051034)) //Contorl Flags
#define P_SPU_Threshold ((UV32 *)(0x88051038)) //Compressor Control
#define P_SPU_ChStsL ((UV32 *)(0x8805103C)) //Channel Status
#define P_SPU_WaveInL ((UV32 *)(0x88051040)) //Left Channel Mixer Input
#define P_SPU_WaveInR ((UV32 *)(0x88051044)) //Software Channel FIFO IRQ Threshold
#define P_SPU_WaveOutL ((UV32 *)(0x88051048)) //Left Channel Mixer Outpurput
#define P_SPU_WaveOutR ((UV32 *)(0x8805104C)) //Right Channel Mixer Outpur
#define P_SPU_ChRepeatEnL ((UV32 *)(0x88051050)) //Channel Repeat Enable control
#define P_SPU_ChEnvModeL ((UV32 *)(0x88051054)) //Channel Envelope Mode
#define P_SPU_ChToneReleaseL ((UV32 *)(0x88051058)) //Channel Tone Release Control
#define P_SPU_ChEnvIrqStsL ((UV32 *)(0x8805105C)) //Channel Envelope IRQ Status
#define P_SPU_ChPitchBandEnL ((UV32 *)(0x88051060)) //Channel Pithc Bend Enable
#define P_SPU_CompControl ((UV32 *)(0x88051064)) //Software Channel Phase
#define P_SPU_AttRel ((UV32 *)(0x88051068)) //Attack/Release Time Control
#define P_SPU_EQFreq10 ((UV32 *)(0x8805106C)) //Digital EQ Cut-off Frequency 0/1
#define P_SPU_EQFreq32 ((UV32 *)(0x88051070)) //Digital EQ Cut-off Frequency 2/3
#define P_SPU_EQGain10 ((UV32 *)(0x88051074)) //Digital EQ Gain 0/1
#define P_SPU_EQGain32 ((UV32 *)(0x88051078)) //Digital EQ Gain 2/3
#define P_SPU_BankAddr ((UV32 *)(0x8805107C)) //Wave Table's Bank Address
#define P_SPU_SoftCHBaseL ((UV32 *)(0x88051080)) //Software channel external buffer base address
#define P_SPU_SoftCHBaseH ((UV32 *)(0x88051084)) //Software channel external buffer base address
#define P_SPU_SoftIRQEN ((UV32 *)(0x88051088)) //Software channel FIQ control
#define P_SPU_ChEnH ((UV32 *)(0x88051400)) //Channel Enable
#define P_SPU_ChFiqEnH ((UV32 *)(0x88051408)) //Channel FIQ Enable
#define P_SPU_ChFiqStsH ((UV32 *)(0x8805140C)) //Channel FIQ Status
#define P_SPU_EnvClk4 ((UV32 *)(0x88051418)) //Envelope Interval Select
#define P_SPU_EnvClk5 ((UV32 *)(0x8805141C)) //Envelope Interval Select
//#define P_SPU_EnvClk6 ((UV32 *)(0x88051420))
//#define P_SPU_EnvClk7 ((UV32 *)(0x88051424))
#define P_SPU_ChEnvRampDownH ((UV32 *)(0x88051428)) //Envelope Fase ramp down
#define P_SPU_ChStopStsH ((UV32 *)(0x8805142C)) //Stop channel status
#define P_SPU_ChZeroCrossEnH ((UV32 *)(0x88051430)) //Zero cross Enable
#define P_SPU_ChStsH ((UV32 *)(0x8805143C)) //Channel Status
#define P_SPU_ChRepeatEnH ((UV32 *)(0x88051450)) //Channel Repeat Enable contorl
#define P_SPU_ChEnvModeH ((UV32 *)(0x88051454)) //Channel Envelope Mode
#define P_SPU_ChToneReleaseH ((UV32 *)(0x88051458)) //Channel Tone Release Control
#define P_SPU_ChEnvIrqStsH ((UV32 *)(0x8805145C)) //Channel Envelope IRQ Status
#define P_SPU_ChPitchBandEnH ((UV32 *)(0x88051460)) //Channel Pitch Bend Enable
//****************************************
//SPU Channel Internal Attribute SRAM *
//****************************************
//Must can be used in Value and Pointer.
#define P_SPU_CH_WaveAddr ((U32 *)(0x88050000)) //Wave Address
#define P_SPU_CH_Mode ((U32 *)(0x88050004)) //Mode
#define P_SPU_CH_LoopAddr ((U32 *)(0x88050008)) //Loop Address
#define P_SPU_CH_Pan ((U32 *)(0x8805000C)) //Pan
#define P_SPU_CH_Envelop0 ((U32 *)(0x88050010)) //Envelope0
#define P_SPU_CH_EnvelopData ((U32 *)(0x88050014)) //Envelope Data
#define P_SPU_CH_Envelop1 ((U32 *)(0x88050018)) //Envelope1
#define P_SPU_CH_EnvelopSegment ((U32 *)(0x8805001C)) //Envelope Address
#define P_SPU_CH_EnvelopOffset ((U32 *)(0x88050020)) //Envelope Address
#define P_SPU_CH_WaveData0 ((U32 *)(0x88050024)) //Wave Data 0
#define P_SPU_CH_EnvelopLoop ((U32 *)(0x88050028)) //Envelope Loop Control
#define P_SPU_CH_WaveData ((U32 *)(0x8805002C)) //Wave Data
#define P_SPU_CH_AdpcmSel ((U32 *)(0x88050034)) //ADPCM Selection
//Register Offset from each channel's P_ChWaveAddr
#define D_SPU_CH_WaveAddr (0x000 ) //P_ChWaveAddr
#define D_SPU_CH_Mode (0x001 ) //P_ChMode - P_ChWaveAddr
#define D_SPU_CH_LoopAddr (0x002 ) //P_ChLoopAddr - P_ChWaveAddr
#define D_SPU_CH_Pan (0x003 ) //P_ChPan - P_ChWaveAddr
#define D_SPU_CH_Envelop0 (0x004 ) //P_ChEnvelop0 - P_ChWaveAddr
#define D_SPU_CH_EnvelopData (0x005 ) //P_ChEnvelopData - P_ChWaveAddr
#define D_SPU_CH_Envelop1 (0x006 ) //P_ChEnvelop1 - P_ChWaveAddr
#define D_SPU_CH_EnvelopSegment (0x007 ) //P_ChEnvelopSeg - P_ChWaveAddr
#define D_SPU_CH_EnvelopOffset (0x008 ) //P_ChEnvelopOffset - P_ChWaveAddr
#define D_SPU_CH_WaveData0 (0x009 ) //P_ChWaveData0 - P_ChWaveAddr
#define D_SPU_CH_EnvelopLoop (0x00A ) //P_ChEnvelopLoop - P_ChWaveAddr
#define D_SPU_CH_WaveData (0x00B ) //P_ChWaveData1 - P_ChWaveAddr
#define D_SPU_CH_AdpcmSel (0x00D ) //P_ChAdpcmSel - P_ChWaveAddr
//****************************************
//SPU Channel Internal Phase SRAM *
//****************************************
//Must can be used in Value and Pointer.
#define P_SPU_CH_Phase ((U32 *)(0x88050800)) //Phase
#define P_SPU_CH_PhaseAccumulator ((U32 *)(0x88050804)) //Phase Accumulator
#define P_SPU_CH_TargetPhase ((U32 *)(0x88050808)) //Target Phase
#define P_SPU_CH_PhaseControl ((U32 *)(0x8805080C)) //Phase Control
//Register Offset from each channel's P_ChPhase
#define D_SPU_CH_PhaseAccumulator (0x0001 ) //P_ChPhaseAccumulator - P_ChPhase
#define D_SPU_CH_TargetPhase (0x0002 ) //P_ChTargetPhase - P_ChPhase
#define D_SPU_CH_PhaseControl (0x0003 ) //P_ChPhaseControl - P_ChPhase
/**
* CD: 0x0806_0000 ~ 0x0806_FFFF
*/
#define CDBASE 0x88060000
#define P_IF51_CONFIG (UV32*)(CDBASE + 0x00000000)
#define P_IF51_ADDR (UV32*)(CDBASE + 0x00000004)
#define P_IF51_DATA (UV32*)(CDBASE + 0x00000008)
#define P_IF51_CONTROL (UV32*)(CDBASE + 0x0000000C)
#define P_CDDSP_CONFIG (UV32*)(CDBASE + 0x00000040)
#define P_CDDSP_CONTROL (UV32*)(CDBASE + 0x00000044)
#define P_CDDSP_SEEK_MM (UV32*)(CDBASE + 0x00000048)
#define P_CDDSP_SEEK_SS (UV32*)(CDBASE + 0x0000004C)
#define P_CDDSP_SEEK_FF (UV32*)(CDBASE + 0x00000050)
#define P_CDDSP_STATUS (UV32*)(CDBASE + 0x00000054)
#define P_CD_BUF_BTM_ADDR (UV32*)(CDBASE + 0x00000060)
#define P_CD_BUF_TOP_ADDR (UV32*)(CDBASE + 0x00000064)
#define P_CD_WRITE_PTR (UV32*)(CDBASE + 0x00000068)
#define P_CD_FRAME_SIZE (UV32*)(CDBASE + 0x0000006C)
#define P_CD_FRAME_CNT (UV32*)(CDBASE + 0x00000070)
#define P_CD_CONFIG (UV32*)(CDBASE + 0x00000080)
#define P_CD_CONTROL (UV32*)(CDBASE + 0x00000084)
/**
* MIU1: 0x0807_0000 ~ 0x0807_FFFF
*/
#define MIU1BASE 0x88070000
#define P_TV_START_ADR1 (UV32*)(MIU1BASE + 0x00000000)
#define P_TV_START_ADR2 (UV32*)(MIU1BASE + 0x00000004)
#define P_TV_START_ADR3 (UV32*)(MIU1BASE + 0x00000008)
#define P_LCD_START_ADR1 (UV32*)(MIU1BASE + 0x0000000C)
#define P_LCD_START_ADR2 (UV32*)(MIU1BASE + 0x00000010)
#define P_LCD_START_ADR3 (UV32*)(MIU1BASE + 0x00000014)
#define P_SPU_START_ADR (UV32*)(MIU1BASE + 0x00000054)
#define P_SDRAM_POWER_DOWN (UV32*)(MIU1BASE + 0x0000005C)
#define P_MIU1_SDRAM_SETTING (UV32*)(MIU1BASE + 0x00000060)
#define P_MIU1_STATUS (UV32*)(MIU1BASE + 0x0000006C)
#define P_MP4RAW_START_ADR1 (UV32*)(MIU1BASE + 0x00000070)
#define P_MP4RAW_START_ADR2 (UV32*)(MIU1BASE + 0x00000074)
#define P_MP4RAW_START_ADR3 (UV32*)(MIU1BASE + 0x00000078)
#define P_MP4W_START_ADR1 (UV32*)(MIU1BASE + 0x0000007c)
#define P_MP4W_START_ADR2 (UV32*)(MIU1BASE + 0x00000080)
#define P_MP4W_START_ADR3 (UV32*)(MIU1BASE + 0x00000084)
#define P_MP4V_START_ADR1 (UV32*)(MIU1BASE + 0x00000088)
#define P_MP4V_START_ADR2 (UV32*)(MIU1BASE + 0x0000008c)
#define P_MP4_FRAME_BUF_HSIZE (UV32*)(MIU1BASE + 0x00000090)
#define P_SDRAM_SETTING2 (UV32*)(MIU1BASE + 0x00000094)
/**
* APBDMA: 0x0808_0000 ~ 0x0808_FFFF
*/
#define DMABASE 0x88080000
#define P_DMA_BSY (UV32*)(DMABASE + 0x00000000)
#define P_DMA_INT (UV32*)(DMABASE + 0x00000004)
#define P_DMA_AHB_SA1A (UV32*)(DMABASE + 0x00000008)
#define P_DMA_AHB_SA2A (UV32*)(DMABASE + 0x0000000c)
#define P_DMA_AHB_SA3A (UV32*)(DMABASE + 0x00000010)
#define P_DMA_AHB_SA4A (UV32*)(DMABASE + 0x00000014)
#define P_DMA_AHB_EA1A (UV32*)(DMABASE + 0x00000018)
#define P_DMA_AHB_EA2A (UV32*)(DMABASE + 0x0000001c)
#define P_DMA_AHB_EA3A (UV32*)(DMABASE + 0x00000020)
#define P_DMA_AHB_EA4A (UV32*)(DMABASE + 0x00000024)
#define P_DMA_APB_SA1 (UV32*)(DMABASE + 0x00000028)
#define P_DMA_APB_SA2 (UV32*)(DMABASE + 0x0000002c)
#define P_DMA_APB_SA3 (UV32*)(DMABASE + 0x00000030)
#define P_DMA_APB_SA4 (UV32*)(DMABASE + 0x00000034)
#define P_DMA_AHB_SA1B (UV32*)(DMABASE + 0x0000004C)
#define P_DMA_AHB_SA2B (UV32*)(DMABASE + 0x00000050)
#define P_DMA_AHB_SA3B (UV32*)(DMABASE + 0x00000054)
#define P_DMA_AHB_SA4B (UV32*)(DMABASE + 0x00000058)
#define P_DMA_AHB_EA1B (UV32*)(DMABASE + 0x0000005C)
#define P_DMA_AHB_EA2B (UV32*)(DMABASE + 0x00000060)
#define P_DMA_AHB_EA3B (UV32*)(DMABASE + 0x00000064)
#define P_DMA_AHB_EA4B (UV32*)(DMABASE + 0x00000068)
#define P_DMA_CR1 (UV32*)(DMABASE + 0x0000006C)
#define P_DMA_CR2 (UV32*)(DMABASE + 0x00000070)
#define P_DMA_CR3 (UV32*)(DMABASE + 0x00000074)
#define P_DMA_CR4 (UV32*)(DMABASE + 0x00000078)
#define P_DMA_RST (UV32*)(DMABASE + 0x0000007C)
/**
* BUFCTL: 0x0809_0000 ~ 0x0809_FFFF
*/
#define BUFBASE 0x88090000
#define P_C2P_SETTING (UV32*)(BUFBASE + 0x00000000)
#define P_PTR_SETTING (UV32*)(BUFBASE + 0x00000004)
#define P_CSI_BUF_PTR (UV32*)(BUFBASE + 0x00000008)
#define P_TEXT1_BUF_PTR (UV32*)(BUFBASE + 0x0000000C)
#define P_TEXT2_BUF_PTR (UV32*)(BUFBASE + 0x00000010)
#define P_TEXT3_BUF_PTR (UV32*)(BUFBASE + 0x00000014)
#define P_PPU_BUF_PTR (UV32*)(BUFBASE + 0x00000018)
#define P_TVE_BUF_PTR (UV32*)(BUFBASE + 0x00000020)
#define P_LCD_BUF_PTR (UV32*)(BUFBASE + 0x00000024)
#define P_BUFCTL_STATUS (UV32*)(BUFBASE + 0x00000028)
#define P_PPU_FRAME_CNT (UV32*)(BUFBASE + 0x0000002C)
#define P_PPU_FCNT_INC (UV32*)(BUFBASE + 0x00000030)
#define P_TVE_FRAME_CNT (UV32*)(BUFBASE + 0x00000034)
#define P_P2T_SETTING (UV32*)(BUFBASE + 0x0000003C)
#define P_P2L_SETTING (UV32*)(BUFBASE + 0x00000040)
#define P_MP4RAW_BUF_PTR (UV32*)(BUFBASE + 0x00000044)
#define P_MP4W_BUF_PTR (UV32*)(BUFBASE + 0x00000048)
#define P_BUFCTL_SETTING (UV32*)(BUFBASE + 0x0000004C)
#define P_MP4R_BUF_PTR (UV32*)(BUFBASE + 0x00000050)
#define P_MP4V_BUF_PTR (UV32*)(BUFBASE + 0x00000054)
#define P_HW4_SETTING (UV32*)(BUFBASE + 0x00000058)
#define P_FRAMENUM_MP4ENC (UV32*)(BUFBASE + 0x0000005C)
/**
* IRQCTL: 0x080A_0000 ~ 0x080A_FFFF
*/
#define IRQBASE 0x880A0000
#define P_INTPND (UV32*)(IRQBASE + 0x00000000)
#define P_INTPND_H (UV32*)(IRQBASE + 0x00000004)
#define P_I_PMST (UV32*)(IRQBASE + 0x00000008)
#define P_I_PSLV0 (UV32*)(IRQBASE + 0x00000010)
#define P_I_PSLV1 (UV32*)(IRQBASE + 0x00000014)
#define P_I_PSLV2 (UV32*)(IRQBASE + 0x00000018)
#define P_I_PSLV3 (UV32*)(IRQBASE + 0x0000001C)
/**
* LDMDMA: 0x080C_0000 ~ 0x080C_FFFF
*/
#define LDMBASE 0x880c0000
#define P_LDM_CTRL (UV32*)(LDMBASE + 0x00000000)
#define P_LDM_STATUS (UV32*)(LDMBASE + 0x00000004)
#define P_LDM_MIU_START (UV32*)(LDMBASE + 0x00000008)
#define P_LDM_MIU_END (UV32*)(LDMBASE + 0x0000000C)
#define P_LDM_START_ADDR (UV32*)(LDMBASE + 0x00000010)
#define P_LDM_END_ADDR (UV32*)(LDMBASE + 0x00000014)
/**
* BLNDMA: 0x080D_0000 ~ 0x080D_FFFF
*/
#define BLNDMABASE 0x880D0000
#define P_BLNDMA_SRCA_ADDR (UV32*)(BLNDMABASE + 0x00000000)
#define P_BLNDMA_SRCB_ADDR (UV32*)(BLNDMABASE + 0x00000004)
#define P_BLNDMA_DEST_ADDR (UV32*)(BLNDMABASE + 0x00000008)
#define P_BLNDMA_WIDTH_HEIGH (UV32*)(BLNDMABASE + 0x0000000C)
#define P_BLNDMA_FILL_PAT (UV32*)(BLNDMABASE + 0x00000010)
#define P_BLNDMA_CONTROL_1 (UV32*)(BLNDMABASE + 0x00000014)
#define P_BLNDMA_IRQ_CONTROL (UV32*)(BLNDMABASE + 0x00000018)
#define P_BLNDMA_BLEND_FACTOR (UV32*)(BLNDMABASE + 0x0000001C)
#define P_BLNDMA_TRANSPARENT (UV32*)(BLNDMABASE + 0x00000020)
#define P_BLNDMA_ADDR_MODE (UV32*)(BLNDMABASE + 0x00000024)
#define P_BLNDMA_CONTROL_2 (UV32*)(BLNDMABASE + 0x00000028)
#define P_BLNDMA_ABASE_ADDR (UV32*)(BLNDMABASE + 0x00000030)
#define P_BLNDMA_AOFFSET_XY (UV32*)(BLNDMABASE + 0x00000034)
#define P_BLNDMA_A_BG (UV32*)(BLNDMABASE + 0x00000038)
#define P_BLNDMA_BBASE_ADDR (UV32*)(BLNDMABASE + 0x00000040)
#define P_BLNDMA_BOFFSET_XY (UV32*)(BLNDMABASE + 0x00000044)
#define P_BLNDMA_B_BG (UV32*)(BLNDMABASE + 0x00000048)
#define P_BLNDMA_DBASE_ADDR (UV32*)(BLNDMABASE + 0x00000050)
#define P_BLNDMA_DOFFSET_XY (UV32*)(BLNDMABASE + 0x00000054)
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