gtp_dual_1000x.v

Xilinx Virtex5 SGMII高速串行通信例程。

//-----------------------------------------------------------------------------
// Title      : 1000BASE-X RocketIO wrapper
// Project    : Virtex-5 Ethernet MAC Wrappers
//-----------------------------------------------------------------------------
// File       : gtp_dual_1000X.v
// Author     : Xilinx
//-----------------------------------------------------------------------------
// Copyright (c) 2004-2007 by Xilinx, Inc. All rights reserved.
// This text/file contains proprietary, confidential
// information of Xilinx, Inc., is distributed under license
// from Xilinx, Inc., and may be used, copied and/or
// disclosed only pursuant to the terms of a valid license
// agreement with Xilinx, Inc. Xilinx hereby grants you
// a license to use this text/file solely for design, simulation,
// implementation and creation of design files limited
// to Xilinx devices or technologies. Use with non-Xilinx
// devices or technologies is expressly prohibited and
// immediately terminates your license unless covered by
// a separate agreement.
//
// Xilinx is providing this design, code, or information
// "as is" solely for use in developing programs and
// solutions for Xilinx devices. By providing this design,
// code, or information as one possible implementation of
// this feature, application or standard, Xilinx is making no
// representation that this implementation is free from any
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// obtaining any rights you may require for your implementation.
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// but not limited to any warranties or representations that this
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// expressly prohibited.
//
// This copyright and support notice must be retained as part
// of this text at all times. (c) Copyright 2004-2007 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------
// Description:  This is the Verilog instantiation of a Virtex-5 GTP    
//               RocketIO tile for the Embedded Ethernet MAC.
//
//               Two GTP's must be instantiated regardless of how many  
//               GTPs are used in the MGT tile. 
//----------------------------------------------------------------------

`timescale 1 ps / 1 ps

module GTP_dual_1000X
(
          RESETDONE_0,
          ENMCOMMAALIGN_0, 
          ENPCOMMAALIGN_0, 
          LOOPBACK_0, 
          RXUSRCLK_0,
          RXUSRCLK2_0,
          RXRESET_0,          
          TXCHARDISPMODE_0, 
          TXCHARDISPVAL_0, 
          TXCHARISK_0, 
          TXDATA_0, 
          TXUSRCLK_0, 
          TXUSRCLK2_0, 
          TXRESET_0, 
          RXCHARISCOMMA_0, 
          RXCHARISK_0,
          RXCLKCORCNT_0,           
          RXCOMMADET_0, 
          RXDATA_0, 
          RXDISPERR_0, 
          RXNOTINTABLE_0,
          RXREALIGN_0, 
          RXRUNDISP_0, 
          RXBUFERR_0, 
          TXBUFERR_0, 
          PLLLKDET_0, 
          TXOUTCLK_0, 
          TXRUNDISP_0, 
          RXELECIDLE_0,
          TX1N_0, 
          TX1P_0,
          RX1N_0, 
          RX1P_0,

          TX1N_1_UNUSED,
          TX1P_1_UNUSED,
          RX1N_1_UNUSED,
          RX1P_1_UNUSED,


          CLK_DS,
          REFCLKOUT,
          PMARESET,
          DCM_LOCKED);

  output          RESETDONE_0;
  input           ENMCOMMAALIGN_0; 
  input           ENPCOMMAALIGN_0; 
  input           LOOPBACK_0; 
  input           RXUSRCLK_0;
  input           RXUSRCLK2_0;
  input           RXRESET_0;          
  input           TXCHARDISPMODE_0; 
  input           TXCHARDISPVAL_0; 
  input           TXCHARISK_0; 
  input [7:0]     TXDATA_0; 
  input           TXUSRCLK_0; 
  input           TXUSRCLK2_0; 
  input           TXRESET_0; 
  output          RXCHARISCOMMA_0; 
  output          RXCHARISK_0;
  output [2:0]    RXCLKCORCNT_0;           
  output          RXCOMMADET_0; 
  output [7:0]    RXDATA_0; 
  output          RXDISPERR_0; 
  output          RXNOTINTABLE_0;
  output          RXREALIGN_0; 
  output          RXRUNDISP_0; 
  output          RXBUFERR_0; 
  output          TXBUFERR_0; 
  output          PLLLKDET_0; 
  output          TXOUTCLK_0; 
  output          TXRUNDISP_0; 
  output          RXELECIDLE_0;
  output          TX1N_0; 
  output          TX1P_0;
  input           RX1N_0; 
  input           RX1P_0;

  output          TX1N_1_UNUSED;
  output          TX1P_1_UNUSED;
  input           RX1N_1_UNUSED;
  input           RX1P_1_UNUSED;


  input           CLK_DS;
  output          REFCLKOUT;
  input           PMARESET;
  input           DCM_LOCKED;

  //--------------------------------------------------------------------
  // Signal declarations for GTP
  //--------------------------------------------------------------------

   wire PLLLOCK;

            
   wire RXNOTINTABLE_0_INT;   
   wire [7:0] RXDATA_0_INT;
   wire RXCHARISK_0_INT;   
   wire RXDISPERR_0_INT;
   wire RXRUNDISP_0_INT;
         
   wire RXCHARISCOMMA_float0;
   wire RXCHARISK_float0;
   wire [7:0] RXDATA_float0;
   wire RXDISPERR_float0;
   wire RXNOTINTABLE_float0;
   wire RXRUNDISP_float0;
   wire TXKERR_float0;
   wire TXRUNDISP_float0;
   wire [1:0] RXBUFSTATUS_float0;
   wire TXBUFSTATUS_float0;

   wire gt_txoutclk1_0;

   reg  [7:0] RXDATA_0;
   reg  RXRUNDISP_0;
   reg  RXCHARISK_0;

   wire rxelecidlereset0_i;
   wire rxelecidle0_i;
   wire resetdone0_i;
   wire rxenelecidleresetb_i;

   wire RXRECCLK_0;
   wire RXRECCLK_0_BUFR;
   wire RXCHARISCOMMA_0_REC;
   wire RXNOTINTABLE_0_REC;   
   wire [7:0] RXDATA_0_REC;
   wire RXCHARISK_0_REC;   
   wire RXDISPERR_0_REC;
   wire RXRUNDISP_0_REC;

   reg  RXRESET_0_REG;
   reg  RXRESET_0_REC;
   reg  ENPCOMMAALIGN_0_REG;
   reg  ENPCOMMAALIGN_0_REC;
   reg  ENMCOMMAALIGN_0_REG;
   reg  ENMCOMMAALIGN_0_REC;
   wire RXBUFERR_0_REC;
   wire RXBUFERR_0_INT;

   // synthesis attribute ASYNC_REG of RXRESET_0_REG       is "TRUE";
   // synthesis attribute ASYNC_REG of RXRESET_0_REC       is "TRUE";
   // synthesis attribute ASYNC_REG of ENPCOMMAALIGN_0_REG is "TRUE";
   // synthesis attribute ASYNC_REG of ENPCOMMAALIGN_0_REC is "TRUE";
   // synthesis attribute ASYNC_REG of ENMCOMMAALIGN_0_REG is "TRUE";
   // synthesis attribute ASYNC_REG of ENMCOMMAALIGN_0_REC is "TRUE";

   wire pma_reset_i;
   reg  [3:0] reset_r;
   wire refclk_out;
   // synthesis attribute ASYNC_REG of reset_r             is "TRUE";

   //--------------------------------------------------------------------
   // Wait for both PLL's to lock   
   //--------------------------------------------------------------------

   
   assign PLLLKDET_0        =   PLLLOCK;


   //--------------------------------------------------------------------
   // Wire internal signals to outputs   
   //--------------------------------------------------------------------

   assign RXNOTINTABLE_0  =   RXNOTINTABLE_0_INT;
   assign RXDISPERR_0     =   RXDISPERR_0_INT;
   assign TXOUTCLK_0      =   gt_txoutclk1_0;

   assign rxelecidlereset0_i   = rxelecidle0_i & resetdone0_i;
   assign rxenelecidleresetb_i = ~(rxelecidlereset0_i);
   assign RESETDONE_0  = resetdone0_i;
   assign RXELECIDLE_0 = rxelecidle0_i;

  
 

   assign REFCLKOUT = refclk_out;

   //--------------------------------------------------------------------
   // RocketIO PMA reset circuitry
   //--------------------------------------------------------------------
   always@(posedge PMARESET, posedge refclk_out)
   begin
     if (PMARESET == 1'b1)
     begin
       reset_r <= 4'b1111;
     end
     else
     begin
       reset_r <= {reset_r[2:0], PMARESET};
     end
   end
   
   assign pma_reset_i = reset_r[3];

   //--------------------------------------------------------------------
   // Instantiate the Virtex-5 GTP
   // EMAC0 connects to GTP 0 and EMAC1 connects to GTP 1
   //--------------------------------------------------------------------

   GTP_DUAL GTP_1000X 
   (
		.DO                       (),
		.DRDY                     (),
		.PLLLKDET                 (PLLLOCK),
		.REFCLKOUT                (refclk_out),
		.CLKIN                    (CLK_DS),
		.DADDR                    (7'b0000000),
		.DCLK                     (1'b0),
		.DEN                      (1'b0),
		.DI                       (16'b0000000000000000),
		.DWE                      (1'b0),
		.GTPRESET                 (pma_reset_i),
		.INTDATAWIDTH             (1'b1),
		.PLLLKDETEN               (1'b1),
		.PLLPOWERDOWN             (1'b0),
		.REFCLKPWRDNB             (1'b1),
		.TXENPMAPHASEALIGN        (1'b0),
		.TXPMASETPHASE            (1'b0),
		.GTPTEST                  (4'b0000),
		.RXENELECIDLERESETB       (rxenelecidleresetb_i),
        // Connect 0 to EMAC0
		.PHYSTATUS0               (),
		.RESETDONE0               (resetdone0_i),
		.RXBYTEISALIGNED0         (),
		.RXCHANBONDSEQ0           (),
		.RXCHANISALIGNED0         (),
		.RXCHANREALIGN0           (),
		.RXCHBONDO0               (),
		.RXCOMMADET0              (RXCOMMADET_0),
		.RXELECIDLE0              (rxelecidle0_i),
		.RXLOSSOFSYNC0            (),
		.RXOVERSAMPLEERR0         (),
		.RXPRBSERR0               (),
		.RXRECCLK0                (RXRECCLK_0),
		.RXRUNDISP0               ({RXRUNDISP_float0, RXRUNDISP_0_REC}),
		.RXNOTINTABLE0            ({RXNOTINTABLE_float0, RXNOTINTABLE_0_REC}),
		.RXDISPERR0               ({RXDISPERR_float0, RXDISPERR_0_REC}),
		.RXDATA0                  ({RXDATA_float0, RXDATA_0_REC}),
		.RXCHARISK0               ({RXCHARISK_float0, RXCHARISK_0_REC}),
		.RXCHARISCOMMA0           ({RXCHARISCOMMA_float0, RXCHARISCOMMA_0_REC}),
		.RXBUFSTATUS0             ({RXBUFERR_0_REC, RXBUFSTATUS_float1}),
		.RXCLKCORCNT0             (),
		
		.RXBYTEREALIGN0           (RXREALIGN_0),
		.RXSTATUS0                (),
		.RXVALID0                 (),
		.TXBUFSTATUS0             ({TXBUFERR_0, TXBUFSTATUS_float0}),
		.TXKERR0                  (),
		.TXN0                     (TX1N_0),
		.TXOUTCLK0                (gt_txoutclk1_0),
		.TXP0                     (TX1P_0),
		.TXRUNDISP0               ({TXRUNDISP_float0, TXRUNDISP_0}),
		.LOOPBACK0                ({2'b00, LOOPBACK_0}),
		.PRBSCNTRESET0            (1'b0),
		.RXBUFRESET0              (RXRESET_0_REC),
		.RXRESET0                 (RXRESET_0_REC),