routed.v

Xilinx Virtex5 SGMII高速串行通信例程。

  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N45 ;
  wire \ProtoComp55.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N44 ;
  wire \ProtoComp55.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N43 ;
  wire \ProtoComp55.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_pipe_mux0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_eof_bram_0_and0000_norst ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N26 ;
  wire \ProtoComp59.CYINITVCC.1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N25 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N24 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N23 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N30 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N29 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N28 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N27 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N34 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N33 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N32 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N31 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_state_FFd3-In ;
  wire \v5_emac_ll/N328 ;
  wire \v5_emac_ll/N329 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N47 ;
  wire \ProtoComp248.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<3>_rt_184 ;
  wire \ProtoComp248.D5LUT.O5 ;
  wire \ProtoComp248.CYINITGND.0 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<2>_rt_185 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<1>_rt_186 ;
  wire \ProtoComp248.C5LUT.O5 ;
  wire \ProtoComp248.B5LUT.O5 ;
  wire \ProtoComp249.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<6>_rt_187 ;
  wire \ProtoComp249.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<5>_rt_188 ;
  wire \ProtoComp249.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<4>_rt_189 ;
  wire \ProtoComp249.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<7>_rt_190 ;
  wire \ProtoComp79.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<8>_rt_191 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<9>_rt_192 ;
  wire \ProtoComp79.B5LUT.O5 ;
  wire \ProtoComp79.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<10>_rt_193 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<11>_rt_194 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_state_FFd1-In ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_state_FFd2-In ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<3>_rt_195 ;
  wire \ProtoComp68.D5LUT.O5 ;
  wire \ProtoComp68.CYINITGND.0 ;
  wire \ProtoComp68.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<1>_rt_196 ;
  wire \ProtoComp68.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<2>_rt_197 ;
  wire \ProtoComp68.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<7>_rt_198 ;
  wire \ProtoComp69.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<6>_rt_199 ;
  wire \ProtoComp69.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<5>_rt_200 ;
  wire \ProtoComp69.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<4>_rt_201 ;
  wire \ProtoComp69.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<9>_rt_202 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer<8>_rt_203 ;
  wire \ProtoComp70.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_0_204 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_3_205 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_2_206 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_1_207 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_5_208 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_4_209 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_7_210 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_data_bram_6_211 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/even_mux0000 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<2>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<0>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N37 ;
  wire \v5_emac_ll/N304 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N46 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N45 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N44 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N43_rt_212 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_frames<0>_rt_213 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N50 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N49 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N48 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N47 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N51 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N33 ;
  wire \ProtoComp56.CYINITVCC.1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N32 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N31 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N30 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N37 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N36 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N35 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N34 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N41 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N40 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N39 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N38 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxrundisp_usr_mux0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_tran_frame_tog_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N5 ;
  wire \ProtoComp71.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr3 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N4 ;
  wire \ProtoComp71.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N3 ;
  wire \ProtoComp71.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N2 ;
  wire \ProtoComp71.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N9 ;
  wire \ProtoComp72.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr7 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr6 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr4 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N8 ;
  wire \ProtoComp72.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N7 ;
  wire \ProtoComp72.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N6 ;
  wire \ProtoComp72.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N13 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr11 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr10 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr9 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr8 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N12 ;
  wire \ProtoComp73.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N11 ;
  wire \ProtoComp73.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N10 ;
  wire \ProtoComp73.A5LUT.O5 ;
  wire \v5_emac_ll/v5_emac_block/N302 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<5>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<6>1 ;
  wire \v5_emac_ll/v5_emac_block/N306 ;
  wire \v5_emac_ll/v5_emac_block/N305 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<4>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<3>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/wr_addr_gray_2_xor0000 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/wr_addr_gray_1_xor0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_txfer_tog_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_store_frame_tog_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N21 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<3>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<2>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<1>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<0>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N20 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_addr<1>_rt_214 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N18 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_addr<0>_rt_215 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N25 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<7>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<6>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<5>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<4>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N24 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N23 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N22 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N29 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N28 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N26 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N27 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Result<8>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/wr_addr_gray_5_xor0000 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/wr_addr_gray_4_xor0000 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/wr_addr_gray_3_xor0000 ;
  wire \v5_emac_ll/N333 ;
  wire \v5_emac_ll/N334 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd4-In ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_reg_or0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_col_window_pipe_0_and0000_norst ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mshreg_wr_bf_pipe_1_216 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxdata_usr_mux0000<0>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N9 ;
  wire \ProtoComp80.CYINITVCC.1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N8 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N7 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N6 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N12 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N10 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N11 ;
  wire \v5_emac_ll/v5_emac_block/N303 ;
  wire \v5_emac_ll/v5_emac_block/N304 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_cmp_eq0004 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd2-In_217 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd3-In ;
  wire \v5_emac_ll/N326 ;
  wire \v5_emac_ll/N327 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxdata_usr_mux0000<1>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxdata_usr_mux0000<2>1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N16 ;
  wire \ProtoComp88.CYINITVCC.1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/N15 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_i