routed.v

Xilinx Virtex5 SGMII高速串行通信例程。

  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXRUNDISP10 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXRUNDISP11 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHARISK10 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHARISK11 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDISPERR10 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDISPERR11 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXNOTINTABLE10 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXNOTINTABLE11 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA10 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA11 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA12 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA13 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA14 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA15 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA16 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA17 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA18 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA19 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA110 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA111 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA112 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA113 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA114 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA115 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHARISCOMMA01 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXRUNDISP01 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHARISK01 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDISPERR01 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXNOTINTABLE01 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA08 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA09 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA010 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA011 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA012 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA013 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA014 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXDATA015 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXOVERSAMPLEERR1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXOVERSAMPLEERR0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/DRDY ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXPRBSERR1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXPRBSERR0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXELECIDLE1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/PHYSTATUS1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/PHYSTATUS0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHANISALIGNED1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHANREALIGN1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHANBONDSEQ1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXBYTEISALIGNED1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXBYTEREALIGN1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCOMMADET1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHANISALIGNED0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHANREALIGN0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCHANBONDSEQ0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXBYTEISALIGNED0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXBYTEREALIGN0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXCOMMADET0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RESETDONE1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXVALID1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXVALID0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/TXOUTCLK1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXRECCLK1 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/TXOUTCLK0 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXUSRCLK20_INT ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/RXUSRCLK0_INT ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/TXUSRCLK20_INT ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/GTP_1000X/TXUSRCLK0_INT ;
  wire \CLIENTEMAC0TXIFGDELAY<0>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<1>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<2>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<3>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<4>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<5>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<6>/INBUF_B ;
  wire \CLIENTEMAC0TXIFGDELAY<7>/INBUF_B ;
  wire \PHYAD_0<0>/INBUF_B ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_src_rdy_n_mux0000 ;
  wire \client_side_asm_emac0/Mshreg_rdy_sr_content_6_148 ;
  wire \client_side_asm_emac0/Mshreg_eof_sr_content_6_149 ;
  wire \client_side_asm_emac0/Mshreg_sof_sr_content_6_150 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_3_151 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_2_152 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_1_153 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_0_154 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_7_155 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_state_FFd2-In ;
  wire \client_side_asm_emac0/control_fsm_state_FFd3-In ;
  wire \client_side_asm_emac0/control_fsm_state_FFd2-In ;
  wire \client_side_asm_emac0/control_fsm_state_FFd1-In ;
  wire \client_side_asm_emac0/Mshreg_sof_sr_content_4_156 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_5_157 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_4_158 ;
  wire \client_side_asm_emac0/Mshreg_data_sr_content_5_6_159 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_6_160 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_5_161 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_7_162 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_3_163 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_2_164 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_1_165 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_0_166 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_state_FFd1-In_167 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_eof_state ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_accept_pipe_0_and0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_4 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_3 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_7 ;
  wire \client_side_asm_emac0/Mshreg_eof_sr_content_4_168 ;
  wire \v5_emac_ll/Mshreg_RX_LL_DATA_0_4_169 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_6_170 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_8 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_sof_n_mux0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_0 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_eqn_2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_retran_frame_tog_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N5 ;
  wire \ProtoComp62.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr3 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N4 ;
  wire \ProtoComp62.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N3 ;
  wire \ProtoComp62.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N2 ;
  wire \ProtoComp62.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N9 ;
  wire \ProtoComp63.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr7 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr6 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr4 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N8 ;
  wire \ProtoComp63.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N7 ;
  wire \ProtoComp63.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N6 ;
  wire \ProtoComp63.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N13 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr11 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr10 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr9 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr8 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N12 ;
  wire \ProtoComp64.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N11 ;
  wire \ProtoComp64.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N10 ;
  wire \ProtoComp64.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N52 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N51 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N50 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N49 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_frames<0>_rt_171 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N56 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N55 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N54 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N53 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N57 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<3>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<2>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<1>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<0>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/_mux0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_eof_mux0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<3>_rt_172 ;
  wire \ProtoComp74.D5LUT.O5 ;
  wire \ProtoComp74.CYINITGND.0 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<2>_rt_173 ;
  wire \ProtoComp74.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<1>_rt_174 ;
  wire \ProtoComp74.B5LUT.O5 ;
  wire \ProtoComp74.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<7>_rt_175 ;
  wire \ProtoComp75.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<6>_rt_176 ;
  wire \ProtoComp75.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<5>_rt_177 ;
  wire \ProtoComp75.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<4>_rt_178 ;
  wire \ProtoComp75.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<11>_rt_179 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<10>_rt_180 ;
  wire \ProtoComp76.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<9>_rt_181 ;
  wire \ProtoComp76.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr<8>_rt_182 ;
  wire \ProtoComp76.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N38 ;
  wire \ProtoComp53.D5LUT.O5 ;
  wire \ProtoComp53.CYINITVCC.1 ;
  wire \v5_emac_ll/N295 ;
  wire \ProtoComp53.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N36 ;
  wire \ProtoComp53.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr<0>_rt_183 ;
  wire \ProtoComp53.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N42 ;
  wire \ProtoComp54.D5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N41 ;
  wire \ProtoComp54.C5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N40 ;
  wire \ProtoComp54.B5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N39 ;
  wire \ProtoComp54.A5LUT.O5 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N46 ;