routed.v

Xilinx Virtex5 SGMII高速串行通信例程。

  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/next_rd_addr[2] ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/next_rd_addr[3] ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/next_rd_addr[4] ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/next_rd_addr[5] ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/next_rd_addr[6] ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/Result<1>1_68 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_full_or0000_69 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_bram_u_70 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N43 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_store_frame_71 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxchariscomma_usr_72 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxchariscomma_usr_and0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_tran_frame_tog_73 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_tran_frame_tog_74 ;
  wire \v5_emac_ll/v5_emac_block/rxbuferr_0_i ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxbuferr_75 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXBUFERR_0_REC ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_ovflow_dst_rdy_or0000_76 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_col_window_expire_77 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_eof_state_reg_78 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N42 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_retran_frame_tog_79 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_retran_frame_tog_80 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Msub_rd_dec_addr_sub0000_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Msub_rd_dec_addr_sub0000_cy[7] ;
  wire \v5_emac_ll/N300 ;
  wire \v5_emac_ll/N298 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Msub_wr_addr_diff_sub0000_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Msub_wr_addr_diff_sub0000_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Msub_wr_addr_diff_sub0000_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Msub_wr_addr_diff_sub0000_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/overflow_inv ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_addr_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Maccum_rd_addr_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Maccum_rd_addr_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_rd_slot_timer_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_rd_slot_timer_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_reload_inv ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_wr_addr_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N35 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_start_addr_load ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Madd_wr_start_addr_add0000_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Madd_wr_start_addr_add0000_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Madd_rd_addr_addsub0000_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Madd_rd_addr_addsub0000_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<0>2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<1>2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<2>2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<3>2 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<4>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<5>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<6>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Mcount_wr_frames_cy[7] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<7>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/Result<8>1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_frames_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_rd_frames_cy[3] ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Mcount_rd_frames_cy[7] ;
  wire EMAC0CLIENTTXSTATSBYTEVLD_OBUF_81;
  wire PHY_RESET_0_OBUF_82;
  wire EMAC0ANINTERRUPT_OBUF_83;
  wire EMAC0CLIENTSYNCACQSTATUS_OBUF_84;
  wire EMAC0CLIENTRXFRAMEDROP_OBUF_85;
  wire EMAC0CLIENTTXSTATS_OBUF_86;
  wire EMAC0CLIENTRXSTATS_0_OBUF_87;
  wire EMAC0CLIENTRXDVLD_OBUF_88;
  wire EMAC0CLIENTRXSTATS_1_OBUF_89;
  wire EMAC0CLIENTRXSTATS_2_OBUF_90;
  wire EMAC0CLIENTRXSTATS_3_OBUF_91;
  wire EMAC0CLIENTRXSTATS_4_OBUF_92;
  wire EMAC0CLIENTRXSTATS_5_OBUF_93;
  wire EMAC0CLIENTRXSTATS_6_OBUF_94;
  wire EMAC0CLIENTRXSTATSVLD_OBUF_95;
  wire EMAC0CLIENTTXSTATSVLD_OBUF_96;
  wire EMAC0CLIENTRXSTATSBYTEVLD_OBUF_97;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_en_u ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_en_l ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_bram_u ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_bram_l ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_eof_bram_l ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_eof_bram_u ;
  wire clk_ds;
  wire client_clk_0_o;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXRECCLK_0 ;
  wire \v5_emac_ll/v5_emac_block/plllock_0_i ;
  wire \v5_emac_ll/v5_emac_block/txbuferr_0_i ;
  wire \v5_emac_ll/rx_bad_frame_0_i ;
  wire \v5_emac_ll/rx_good_frame_0_i ;
  wire \v5_emac_ll/v5_emac_block/loopback_0_i ;
  wire \v5_emac_ll/v5_emac_block/mgt_tx_reset_0_i ;
  wire \v5_emac_ll/v5_emac_block/txchardispmode_0_i ;
  wire \v5_emac_ll/v5_emac_block/txchardispval_0_i ;
  wire \v5_emac_ll/v5_emac_block/txcharisk_0_i ;
  wire clk125_o;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXRUNDISP_0_REC ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXNOTINTABLE_0_REC ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXDISPERR_0_REC ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXCHARISK_0_REC ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXCHARISCOMMA_0_REC ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxbuferr_or0000_98 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/frame_in_fifo_99 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_gf_pipe_1_100 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_full_101 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_bf_pipe_1_102 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_eof_103 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_store_frame_tog_104 ;
  wire \client_side_asm_emac0/control_fsm_state_FFd2_105 ;
  wire \client_side_asm_emac0/control_fsm_state_FFd3_106 ;
  wire \client_side_asm_emac0/data_sr_content_5_0_107 ;
  wire \client_side_asm_emac0/data_sr_content_5_1_108 ;
  wire \client_side_asm_emac0/data_sr_content_5_2_109 ;
  wire \client_side_asm_emac0/data_sr_content_5_3_110 ;
  wire \client_side_asm_emac0/data_sr_content_5_4_111 ;
  wire \client_side_asm_emac0/data_sr_content_5_5_112 ;
  wire \client_side_asm_emac0/data_sr_content_5_6_113 ;
  wire \client_side_asm_emac0/data_sr_content_5_7_114 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_dv_pipe<1>_inv ;
  wire \v5_emac_ll/rx_bad_frame_0_r_115 ;
  wire rx_ll_sof_n_0_i;
  wire \client_side_asm_emac0/data_sr_content_5_and0000 ;
  wire \v5_emac_ll/rx_good_frame_0_r_116 ;
  wire \client_side_asm_emac0/rdy_sr_content_6_117 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_ovflow_dst_rdy_118 ;
  wire \client_side_asm_emac0/sof_sr_content_0_not0001 ;
  wire \client_side_asm_emac0/sof_sr_content_4_119 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N251 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_frames_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N111 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N19 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N81 ;
  wire \client_side_asm_emac0/eof_sr_content_4_120 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_txfer_tog_121 ;
  wire \client_side_asm_emac0/eof_sr_content_6_122 ;
  wire \v5_emac_ll/N139 ;
  wire \v5_emac_ll/N138 ;
  wire \v5_emac_ll/N150 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_ovflow_dst_rdy_not0001_inv ;
  wire tx_ll_eof_n_0_i;
  wire \v5_emac_ll/N305 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_txfer_tog_123 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_0_124 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_1_125 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_2_126 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_3_127 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_4_128 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_5_129 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_6_130 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_1_7_131 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_col_window_pipe_1_132 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_col_window_pipe_0_133 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_frame_in_fifo_or0000_134 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_eof_pipe_0_135 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/insert_idle_or0000_map7 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_0_136 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_1_137 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_2_138 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_3_139 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_4_140 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_5_141 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_6_142 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_data_pipe_0_7_143 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_sof_pipe_0_144 ;
  wire \v5_emac_ll/N131 ;
  wire \client_side_asm_emac0/control_fsm_state_FFd1_145 ;
  wire \v5_emac_ll/N103 ;
  wire \v5_emac_ll/N178 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_tran_frame_delay_146 ;
  wire \v5_emac_ll/N111 ;
  wire \v5_emac_ll/N180 ;
  wire \v5_emac_ll/N113 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/even_mux0000_map16 ;
  wire \v5_emac_ll/N136 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/insert_idle_or0000_map15 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_txfer_tog_delay_147 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_state_cmp_eq0000 ;
  wire \v5_emac_ll/v5_emac_block/N72 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/d16p2_wr ;
  wire \v5_emac_ll/N316 ;
  wire \v5_emac_ll/N315 ;
  wire \v5_emac_ll/v5_emac_block/N63 ;
  wire \CLIENTEMAC0PAUSEVAL<0>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<1>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<2>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<3>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<4>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<5>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<6>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<7>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<8>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<9>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<10>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<11>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<12>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<13>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<14>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEVAL<15>/INBUF_B ;
  wire \CLIENTEMAC0PAUSEREQ/INBUF_B ;
  wire \RESET/INBUF_B ;
  wire \PHYAD_0<1>/INBUF_B ;
  wire \PHYAD_0<2>/INBUF_B ;
  wire \PHYAD_0<3>/INBUF_B ;
  wire \PHYAD_0<4>/INBUF_B ;
  wire \v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/HOSTRDDATA0 ;
  wire \v5_emac_ll/v5_emac_block/v5_emac_wrapper/v5_emac/HOSTRDDATA1 ;