routed.v

Xilinx Virtex5 SGMII高速串行通信例程。

////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: J.33
//  \   \         Application: netgen
//  /   /         Filename: routed.v
// /___/   /\     Timestamp: Tue Apr 17 11:32:26 2007
// \   \  /  \ 
//  \___\/\___\
//             
// Command	: -ofmt verilog -sim -dir . -pcf mapped.pcf -tm v5_emac_v1_2_example_design -w -sdf_anno false routed.ncd routed.v 
// Device	: 5vsx50tff1136-1 (ADVANCED 1.53 2007-03-08)
// Input file	: routed.ncd
// Output file	: C:\ml506_sgmii_design\v5_emac_v1_2\implement\results\routed.v
// # of Modules	: 1
// Design Name	: v5_emac_v1_2_example_design
// Xilinx        : C:\XILINX_91i_J.33.10_SP3
//             
// Purpose:    
//     This verilog netlist is a verification model and uses simulation 
//     primitives which may not represent the true implementation of the 
//     device, however the netlist is functionally correct and should not 
//     be modified. This file cannot be synthesized and should only be used 
//     with supported simulation tools.
//             
// Reference:  
//     Development System Reference Guide, Chapter 23
//     Synthesis and Simulation Design Guide, Chapter 6
//             
////////////////////////////////////////////////////////////////////////////////

`timescale 1 ns/1 ps

module v5_emac_v1_2_example_design (
  EMAC0CLIENTRXSTATSVLD, RXN_1_UNUSED, TXP_0, EMAC0CLIENTTXSTATS, RESET, EMAC0CLIENTRXDVLD, RXN_0, EMAC0CLIENTTXSTATSBYTEVLD, PHY_RESET_0, 
TXP_1_UNUSED, RXP_0, EMAC0CLIENTRXSTATSBYTEVLD, EMAC0CLIENTTXSTATSVLD, RXP_1_UNUSED, EMAC0ANINTERRUPT, EMAC0CLIENTSYNCACQSTATUS, CLIENTEMAC0PAUSEREQ, 
TXN_0, EMAC0CLIENTRXFRAMEDROP, TXN_1_UNUSED, MGTCLK_N, MGTCLK_P, EMAC0CLIENTRXSTATS, CLIENTEMAC0PAUSEVAL, PHYAD_0, CLIENTEMAC0TXIFGDELAY
);
  output EMAC0CLIENTRXSTATSVLD;
  input RXN_1_UNUSED;
  output TXP_0;
  output EMAC0CLIENTTXSTATS;
  input RESET;
  output EMAC0CLIENTRXDVLD;
  input RXN_0;
  output EMAC0CLIENTTXSTATSBYTEVLD;
  output PHY_RESET_0;
  output TXP_1_UNUSED;
  input RXP_0;
  output EMAC0CLIENTRXSTATSBYTEVLD;
  output EMAC0CLIENTTXSTATSVLD;
  input RXP_1_UNUSED;
  output EMAC0ANINTERRUPT;
  output EMAC0CLIENTSYNCACQSTATUS;
  input CLIENTEMAC0PAUSEREQ;
  output TXN_0;
  output EMAC0CLIENTRXFRAMEDROP;
  output TXN_1_UNUSED;
  input MGTCLK_N;
  input MGTCLK_P;
  output [6 : 0] EMAC0CLIENTRXSTATS;
  input [15 : 0] CLIENTEMAC0PAUSEVAL;
  input [4 : 0] PHYAD_0;
  input [7 : 0] CLIENTEMAC0TXIFGDELAY;
  wire NlwRenamedSig_IO_RESET;
  wire NlwRenamedSig_IO_CLIENTEMAC0PAUSEREQ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_en_0 ;
  wire client_clk_0_i;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_1 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_pipe_2 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rd_enable_reg_3 ;
  wire clk125_i;
  wire \v5_emac_ll/v5_emac_block/mgt_rx_reset_0_i ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N231 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_start_addr_load ;
  wire \v5_emac_ll/tx_reset_0_i_4 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rd_enable ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/insert_idle_5 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/insert_idle_reg_6 ;
  wire \v5_emac_ll/v5_emac_block/rxrundisp_0_i ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxnotintable_usr_7 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxrundisp_usr_8 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_store_frame_sync_9 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_store_frame_tog_10 ;
  wire ll_reset_0_i_11;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_bram_u_reg_12 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/N17 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_state_FFd1_13 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/frame_in_fifo_14 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_state_FFd3_15 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_state_FFd2_16 ;
  wire \client_side_asm_emac0/rx_enable ;
  wire \client_side_asm_emac0/eof_sr_content_0_not0001 ;
  wire rx_ll_eof_n_0_i;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_start_addr_sub0000<10>_bdd0 ;
  wire \v5_emac_ll/N145 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXRECCLK_0_BUFR ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/ENMCOMMAALIGN_0_REC ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/ENMCOMMAALIGN_0_REG ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXRESET_0_REC_17 ;
  wire \v5_emac_ll/v5_emac_block/encommaalign_0_i ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_en_l ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_state_FFd3_18 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_state_FFd1_19 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_state_FFd2_20 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_col_window_expire_21 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_transmit_frame ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd1_22 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_eof_reg_23 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd3_24 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd4_25 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_state_FFd2_26 ;
  wire \v5_emac_ll/N148 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxclkcorcnt_FFd2_27 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxclkcorcnt_FFd1_28 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/even_mux0000_map4 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_retran_frame_delay_29 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_retran_frame_sync_30 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_en_u ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/wr_enable ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/remove_idle_31 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/remove_idle_reg_32 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_retransmit_frame_or0000 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/even_33 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/k28p5_rd_cmp_eq0000_34 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/even_mux0000_map9 ;
  wire \v5_emac_ll/N281 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_transmit_frame_35 ;
  wire GLOBAL_LOGIC1;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_transmit_frame_or0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_retransmit_frame_36 ;
  wire \client_side_asm_emac0/rdy_sr_content_0_not0001 ;
  wire rx_ll_src_rdy_n_0_i;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_addr_not0001 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_state_FFd1_37 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_state_FFd2_38 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_accept_bram_39 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/frame_in_fifo_or0000_40 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_accept_pipe_1_41 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_accept_pipe_0_42 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_addr_not0001 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rxenelecidleresetb_i ;
  wire \v5_emac_ll/v5_emac_block/rxelecidle_0_i ;
  wire resetdone_0_i;
  wire \v5_emac_ll/v5_emac_block/signal_detect_0_i ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_start_addr_load ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_start_addr_reload ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr_reload ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N241 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_addr_not0001_43 ;
  wire \v5_emac_ll/N313 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rxelecidlereset0_i ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N311 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxdisperr_usr_44 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxdisperr_usr_or0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_tran_frame_sync_45 ;
  wire \v5_emac_ll/N296 ;
  wire reset_i;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/RXRESET_0_REG_46 ;
  wire GLOBAL_LOGIC0;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/remove_idle_or0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_slot_timer_and0000_inv_47 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_col_window_expire_or0000 ;
  wire \v5_emac_ll/N127 ;
  wire \v5_emac_ll/N126 ;
  wire \v5_emac_ll/N125 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_drop_frame_48 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_retransmit_49 ;
  wire \v5_emac_ll/tx_ack_0_i ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/frame_in_fifo_sync_50 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_frame_in_fifo_51 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_bram_u_reg_52 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_bram_u_53 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_store_frame_delay_54 ;
  wire \v5_emac_ll/v5_emac_block/rxcharisk_0_i ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxcharisk_usr_55 ;
  wire tx_ll_sof_n_0_i;
  wire \client_side_asm_emac0/sof_sr_content_6_56 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_txfer_en ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_txfer_tog_sync_57 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N20 ;
  wire \v5_emac_ll/N122 ;
  wire \v5_emac_ll/tx_data_valid_0_i ;
  wire \v5_emac_ll/tx_retransmit_0_i ;
  wire \v5_emac_ll/tx_collision_0_i ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_dv_pipe_0_58 ;
  wire \v5_emac_ll/rx_data_valid_0_r_59 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_dv_pipe_1_60 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_col_window_expire_inv ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/N48 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_sof_pipe_1_61 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/tx_collision_inv ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/emptying1_62 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/rd_store_frame_or0000 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/remove_idle_or0000_map17 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/remove_idle_or0000_map8 ;
  wire \v5_emac_ll/v5_emac_block/N69 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_fifo_full_63 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_fifo_full_or0000_64 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_txfer_en ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/rxchariscomma_usr_or0000 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/wr_eof_pipe_1_65 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_col_window_pipe_1_66 ;
  wire \v5_emac_ll/client_side_FIFO_emac0/tx_fifo_i/rd_col_window_pipe_0_67 ;
  wire \v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rx_elastic_buffer_inst_0/next_rd_addr[0] ;