mapped.mrp

Xilinx Virtex5 SGMII高速串行通信例程。

Release 9.1.03i Map J.33
Xilinx Mapping Report File for Design 'v5_emac_v1_2_example_design'

Design Information
------------------
Command Line   : map -ol high v5_emac_v1_2_example_design -o mapped.ncd 
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.36 $
Mapped Date    : Tue Apr 17 11:27:22 2007

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Slice Logic Utilization:
  Number of Slice Registers:                   577 out of  32,640    1%
    Number used as Flip Flops:                 577
  Number of Slice LUTs:                        450 out of  32,640    1%
    Number used as logic:                      411 out of  32,640    1%
      Number using O6 output only:             337
      Number using O5 output only:              29
      Number using O5 and O6:                   45
    Number used as Memory:                      31 out of  12,480    1%
      Number used as Shift Register:            31
        Number using O6 output only:            31
    Number used as exclusive route-thru:         8
  Number of route-thrus:                        39 out of  65,280    1%
    Number using O6 output only:                36
    Number using O5 output only:                 2
    Number using O5 and O6:                      1

Slice Logic Distribution:
  Number of occupied Slices:                   294 out of   8,160    3%
  Number of LUT Flip Flop pairs used:          713
    Number with an unused Flip Flop:           136 out of     713   19%
    Number with an unused LUT:                 263 out of     713   36%
    Number of fully used LUT-FF pairs:         314 out of     713   44%
    Number of unique control sets:              62

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                        48 out of     480   10%

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                       3 out of     132    2%
    Number using BlockRAM only:                  3
    Total primitives used:
      Number of 18k BlockRAM used:               5
    Total Memory used (KB):                     90 out of   4,752    1%
  Number of BUFG/BUFGCTRLs:                      2 out of      32    6%
    Number used as BUFGs:                        2
  Number of BUFDSs:                              1 out of       6   16%
  Number of BUFRs:                               1 out of      24    4%
  Number of GTP_DUALs:                           1 out of       6   16%
  Number of TEMACs:                              1 out of       2   50%

Total equivalent gate count for design:  339,889
Additional JTAG gate count for IOBs:  2,784
Peak Memory Usage:  458 MB
Total REAL time to MAP completion:  1 mins 52 secs 
Total CPU time to MAP completion:   1 mins 35 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network v5_emac_ll/RX_LL_FIFO_STATUS_0<3> has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 3
   more times for the following (max. 5 shown):
   v5_emac_ll/RX_LL_FIFO_STATUS_0<2>,
   v5_emac_ll/RX_LL_FIFO_STATUS_0<1>,
   v5_emac_ll/RX_LL_FIFO_STATUS_0<0>
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:1267 - Dangling pins on
   block:<v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rxrecclk0bufr/v5_emac_ll/v5_emac_block/GTP_DUAL_1000X_inst/rxrecc
   lk0bufr>:<BUFR_BUFR>.  Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
   1.050 Volts)
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
  15 block(s) removed
   6 block(s) optimized away
  15 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "v5_emac_ll/RX_LL_FIFO_STATUS_0<3>" is sourceless and has been
removed.
The signal "v5_emac_ll/RX_LL_FIFO_STATUS_0<2>" is sourceless and has been
removed.
The signal "v5_emac_ll/RX_LL_FIFO_STATUS_0<1>" is sourceless and has been
removed.
The signal "v5_emac_ll/RX_LL_FIFO_STATUS_0<0>" is sourceless and has been
removed.
The signal "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_diff_sub0000<1>"
is sourceless and has been removed.
 Sourceless block "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_diff_1"
(SFF) removed.
  The signal "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_diff<1>" is
sourceless and has been removed.
   Sourceless block
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_3_or0000100" (ROM)
removed.
    The signal "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_3_or0000"
is sourceless and has been removed.
     Sourceless block "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_0"
(SFF) removed.
     Sourceless block "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_1"
(SFF) removed.
     Sourceless block "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_2"
(SFF) removed.
     Sourceless block "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_3"
(SFF) removed.
The signal "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_diff_sub0000<0>"
is sourceless and has been removed.
 Sourceless block "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_diff_0"
(SFF) removed.
  The signal "v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_addr_diff<0>" is
sourceless and has been removed.
The signal
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_0_not0001" is
sourceless and has been removed.
The signal
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_1_not0001" is
sourceless and has been removed.
The signal
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_2_not0001" is
sourceless and has been removed.
The signal
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_3_not0001" is
sourceless and has been removed.
The signal
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_3_or0000_map6" is
sourceless and has been removed.
The signal
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_3_or0000_map19" is
sourceless and has been removed.
Unused block
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Msub_wr_addr_diff_sub0000_xor<0>"
(XOR) removed.
Unused block
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/Msub_wr_addr_diff_sub0000_xor<1>"
(XOR) removed.
Unused block
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_0_not00011_INV_0"
(BUF) removed.
Unused block
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_1_not00011_INV_0"
(BUF) removed.
Unused block
"v5_emac_ll/client_side_FIFO_emac0/rx_fifo_i/wr_fifo_status_2_not00011_INV_0"