fifo64.v

FIFO级联

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module FIFO2(clk, rst, datain, pin, wren, rden, dataout, pout, empty, full);
	 input clk;
	 input rst;
	 input [15:0] datain;
	 input [1:0] pin;
    input rden;
	 input wren;
	 
	 output [15:0] dataout;
	 output [1:0] pout;
	 output empty;
	 output full;
/////////////////////////////////////////////////
    wire empty0;
	 wire full1;
	 wire [15:0] dataout0;
	 wire [1:0] pout0;
	 wire en01;
	 assign en01=~(empty0|full1);
	 
    wire empty1;
	 wire full2;
	 wire [15:0] dataout1;
	 wire [1:0] pout1;
	 wire en12;
	 assign en12=~(empty1|full2);
	 
    wire empty2;
	 wire full3;
	 wire [15:0] dataout2;
	 wire [1:0] pout2;
	 wire en23;
	 assign en23=~(empty2|full3);
	 
    wire empty3;
	 wire full4;
	 wire [15:0] dataout3;
	 wire [1:0] pout3;
	 wire en34;
	 assign en34=~(empty3|full4);
	 
    wire empty4;
	 wire full5;
	 wire [15:0] dataout4;
	 wire [1:0] pout4;
	 wire en45;
	 assign en45=~(empty4|full5);
	 
    wire empty5;
	 wire full6;
	 wire [15:0] dataout5;
	 wire [1:0] pout5;
	 wire en56;
	 assign en56=~(empty5|full6);
	 
    wire empty6;
	 wire full7;
	 wire [15:0] dataout6;
	 wire [1:0] pout6;
	 wire en67;
	 assign en67=~(empty6|full7);
	 
    wire empty7;
	 wire full8;
	 wire [15:0] dataout7;
	 wire [1:0] pout7;
	 wire en78;
	 assign en78=~(empty7|full8);
	 
    wire empty8;
	 wire full9;
	 wire [15:0] dataout8;
	 wire [1:0] pout8;
	 wire en89;
	 assign en89=~(empty8|full9);
	 
    wire empty9;
	 wire full10;
	 wire [15:0] dataout9;
	 wire [1:0] pout9;
	 wire en910;
	 assign en910=~(empty9|full10);
	 
    wire empty10;
	 wire full11;
	 wire [15:0] dataout10;
	 wire [1:0] pout10;
	 wire en1011;
	 assign en1011=~(empty10|full11);
	 
    wire empty11;
	 wire full12;
	 wire [15:0] dataout11;
	 wire [1:0] pout11;
	 wire en1112;
	 assign en1112=~(empty11|full12);
	 
    wire empty12;
	 wire full13;
	 wire [15:0] dataout12;
	 wire [1:0] pout12;
	 wire en1213;
	 assign en1213=~(empty12|full13);
	 
    wire empty13;
	 wire full14;
	 wire [15:0] dataout13;
	 wire [1:0] pout13;
	 wire en1314;
	 assign en1314=~(empty13|full14);
	 
    wire empty14;
	 wire full15;
	 wire [15:0] dataout14;
	 wire [1:0] pout14;
	 wire en1415;
	 assign en1415=~(empty14|full15);
	 
    wire empty15;
	 wire full16;
	 wire [15:0] dataout15;
	 wire [1:0] pout15;
	 wire en1516;
	 assign en1516=~(empty15|full16);
	 
    wire empty16;
	 wire full17;
	 wire [15:0] dataout16;
	 wire [1:0] pout16;
	 wire en1617;
	 assign en1617=~(empty16|full17);
	 
    wire empty17;
	 wire full18;
	 wire [15:0] dataout17;
	 wire [1:0] pout17;
	 wire en1718;
	 assign en1718=~(empty17|full18);
	 
    wire empty18;
	 wire full19;
	 wire [15:0] dataout18;
	 wire [1:0] pout18;
	 wire en1819;
	 assign en1819=~(empty18|full19);
	 
    wire empty19;
	 wire full20;
	 wire [15:0] dataout19;
	 wire [1:0] pout19;
	 wire en1920;
	 assign en1920=~(empty19|full20);
	 
    wire empty20;
	 wire full21;
	 wire [15:0] dataout20;
	 wire [1:0] pout20;
	 wire en2021;
	 assign en2021=~(empty20|full21);
	 
    wire empty21;
	 wire full22;
	 wire [15:0] dataout21;
	 wire [1:0] pout21;
	 wire en2122;
	 assign en2122=~(empty21|full22);
	 
    wire empty22;
	 wire full23;
	 wire [15:0] dataout22;
	 wire [1:0] pout22;
	 wire en2223;
	 assign en2223=~(empty22|full23);
	 
    wire empty23;
	 wire full24;
	 wire [15:0] dataout23;
	 wire [1:0] pout23;
	 wire en2324;
	 assign en2324=~(empty23|full24);
	 
    wire empty24;
	 wire full25;
	 wire [15:0] dataout24;
	 wire [1:0] pout24;
	 wire en2425;
	 assign en2425=~(empty24|full25);
	 
    wire empty25;
	 wire full26;
	 wire [15:0] dataout25;
	 wire [1:0] pout25;
	 wire en2526;
	 assign en2526=~(empty25|full26);
	 
    wire empty26;
	 wire full27;
	 wire [15:0] dataout26;
	 wire [1:0] pout26;
	 wire en2627;
	 assign en2627=~(empty26|full27);
	 
    wire empty27;
	 wire full28;
	 wire [15:0] dataout27;
	 wire [1:0] pout27;
	 wire en2728;
	 assign en2728=~(empty27|full28);
	 
    wire empty28;
	 wire full29;
	 wire [15:0] dataout28;
	 wire [1:0] pout28;
	 wire en2829;
	 assign en2829=~(empty28|full29);
	 
    wire empty29;
	 wire full30;
	 wire [15:0] dataout29;
	 wire [1:0] pout29;
	 wire en2930;
	 assign en2930=~(empty29|full30);
	 
    wire empty30;
	 wire full31;
	 wire [15:0] dataout30;
	 wire [1:0] pout30;
	 wire en3031;
	 assign en3031=~(empty30|full31);
		 
    wire empty31;
	 wire full32;
	 wire [15:0] dataout31;
	 wire [1:0] pout31;
	 wire en3132;
	 assign en3132=~(empty31|full32);
 
    wire empty32;
	 wire full33;
	 wire [15:0] dataout32;
	 wire [1:0] pout32;
	 wire en3233;
	 assign en3233=~(empty32|full33);
	 
    wire empty33;
	 wire full34;
	 wire [15:0] dataout33;
	 wire [1:0] pout33;
	 wire en3334;
	 assign en3334=~(empty33|full34);
	 
    wire empty34;
	 wire full35;
	 wire [15:0] dataout34;
	 wire [1:0] pout34;
	 wire en3435;
	 assign en3435=~(empty34|full35);
	 
    wire empty35;
	 wire full36;
	 wire [15:0] dataout35;
	 wire [1:0] pout35;
	 wire en3536;
	 assign en3536=~(empty35|full36);
	 
    wire empty36;
	 wire full37;
	 wire [15:0] dataout36;
	 wire [1:0] pout36;
	 wire en3637;
	 assign en3637=~(empty36|full37);
	 
	 wire empty37;
	 wire full38;
	 wire [15:0] dataout37;
	 wire [1:0] pout37;
	 wire en3738;
	 assign en3738=~(empty37|full38);
	 
	 wire empty38;
	 wire full39;
	 wire [15:0] dataout38;
	 wire [1:0] pout38;
	 wire en3839;
	 assign en3839=~(empty38|full39);
	 
	 wire empty39;
	 wire full40;
	 wire [15:0] dataout39;
	 wire [1:0] pout39;
	 wire en3940;
	 assign en3940=~(empty39|full40);
	 
	 wire empty40;
	 wire full41;
	 wire [15:0] dataout40;
	 wire [1:0] pout40;
	 wire en4041;
	 assign en4041=~(empty40|full41);
	 
	 wire empty41;
	 wire full42;
	 wire [15:0] dataout41;
	 wire [1:0] pout41;
	 wire en4142;
	 assign en4142=~(empty41|full42);
	 
	 wire empty42;
	 wire full43;
	 wire [15:0] dataout42;
	 wire [1:0] pout42;
	 wire en4243;
	 assign en4243=~(empty42|full43);
	 
	 wire empty43;
	 wire full44;
	 wire [15:0] dataout43;
	 wire [1:0] pout43;
	 wire en4344;
	 assign en4344=~(empty43|full44);
	 
	 wire empty44;
	 wire full45;
	 wire [15:0] dataout44;
	 wire [1:0] pout44;
	 wire en4445;
	 assign en4445=~(empty44|full45);
	 
	 wire empty45;
	 wire full46;
	 wire [15:0] dataout45;
	 wire [1:0] pout45;
	 wire en4546;
	 assign en4546=~(empty45|full46);
	 
	 wire empty46;
	 wire full47;
	 wire [15:0] dataout46;
	 wire [1:0] pout46;
	 wire en4647;
	 assign en4647=~(empty46|full47);
	 
	 wire empty47;
	 wire full48;
	 wire [15:0] dataout47;
	 wire [1:0] pout47;
	 wire en4748;
	 assign en4748=~(empty47|full48);
	 
	 wire empty48;
	 wire full49;
	 wire [15:0] dataout48;
	 wire [1:0] pout48;
	 wire en4849;
	 assign en4849=~(empty48|full49);
	 
	 wire empty49;
	 wire full50;
	 wire [15:0] dataout49;
	 wire [1:0] pout49;
	 wire en4950;
	 assign en4950=~(empty49|full50);
	 
	 wire empty50;
	 wire full51;
	 wire [15:0] dataout50;
	 wire [1:0] pout50;
	 wire en5051;
	 assign en5051=~(empty50|full51);
	 
	 wire empty51;
	 wire full52;
	 wire [15:0] dataout51;
	 wire [1:0] pout51;
	 wire en5152;
	 assign en5152=~(empty51|full52);
	 
	 wire empty52;
	 wire full53;
	 wire [15:0] dataout52;
	 wire [1:0] pout52;
	 wire en5253;
	 assign en5253=~(empty52|full53);
	 
	 wire empty53;
	 wire full54;
	 wire [15:0] dataout53;
	 wire [1:0] pout53;
	 wire en5354;
	 assign en5354=~(empty53|full54);
	 
	 wire empty54;
	 wire full55;
	 wire [15:0] dataout54;
	 wire [1:0] pout54;
	 wire en5455;
	 assign en5455=~(empty54|full55);
	 
	 wire empty55;
	 wire full56;
	 wire [15:0] dataout55;
	 wire [1:0] pout55;
	 wire en5556;
	 assign en5556=~(empty55|full56);
	 
	 wire empty56;
	 wire full57;
	 wire [15:0] dataout56;
	 wire [1:0] pout56;
	 wire en5657;
	 assign en5657=~(empty56|full57);
	 
	 wire empty57;
	 wire full58;
	 wire [15:0] dataout57;
	 wire [1:0] pout57;
	 wire en5758;
	 assign en5758=~(empty57|full58);
	 
	 wire empty58;
	 wire full59;
	 wire [15:0] dataout58;
	 wire [1:0] pout58;
	 wire en5859;
	 assign en5859=~(empty58|full59);
	 
	 wire empty59;
	 wire full60;
	 wire [15:0] dataout59;
	 wire [1:0] pout59;
	 wire en5960;
	 assign en5960=~(empty59|full60);
	 
	 wire empty60;
	 wire full61;
	 wire [15:0] dataout60;
	 wire [1:0] pout60;
	 wire en6061;
	 assign en6061=~(empty60|full61);
	 
	 wire empty61;
	 wire full62;
	 wire [15:0] dataout61;
	 wire [1:0] pout61;
	 wire en6162;
	 assign en6162=~(empty61|full62);
	 
	 wire empty62;
	 wire full63;
	 wire [15:0] dataout62;
	 wire [1:0] pout62;
	 wire en6263;
	 assign en6263=~(empty62|full63);	 
	 	 
	 FIFO18 FIFO_INST0(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout0), 
				.DOP(pout0), 
				.EMPTY(empty0), 
				.FULL(full), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(datain), 
				.DIP(pin), 
				.RDCLK(clk), 
				.RDEN(en01), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(wren)
				);

    //parameter ALMOST_EMPTY_OFFSET = 12'h080;
    //parameter ALMOST_FULL_OFFSET = 12'h080;
    defparam FIFO_INST0.DATA_WIDTH = 18;
    //parameter integer DO_REG = 1;
    //defparam FIFO_INST0.EN_SYN = "TRUE";
    defparam FIFO_INST0.FIRST_WORD_FALL_THROUGH = "TRUE";
    //parameter SIM_MODE = "SAFE";
	 
	 FIFO18 FIFO_INST1(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout1), 
				.DOP(pout1), 
				.EMPTY(empty1), 
				.FULL(full1), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout0), 
				.DIP(pout0), 
				.RDCLK(clk), 
				.RDEN(en12), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en01)
				);

    //parameter ALMOST_EMPTY_OFFSET = 12'h080;
    //parameter ALMOST_FULL_OFFSET = 12'h080;
    defparam FIFO_INST1.DATA_WIDTH = 18;
    //parameter integer DO_REG = 1;
    //defparam FIFO_INST0.EN_SYN = "TRUE";
    defparam FIFO_INST1.FIRST_WORD_FALL_THROUGH = "TRUE";
    //parameter SIM_MODE = "SAFE";
	 
	 FIFO18 FIFO_INST2(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout2), 
				.DOP(pout2), 
				.EMPTY(empty2), 
				.FULL(full2), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout1), 
				.DIP(pout1), 
				.RDCLK(clk), 
				.RDEN(en23), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en12)
				);

    //parameter ALMOST_EMPTY_OFFSET = 12'h080;
    //parameter ALMOST_FULL_OFFSET = 12'h080;
    defparam FIFO_INST2.DATA_WIDTH = 18;
    //parameter integer DO_REG = 1;
    //defparam FIFO_INST0.EN_SYN = "TRUE";
    defparam FIFO_INST2.FIRST_WORD_FALL_THROUGH = "TRUE";
    //parameter SIM_MODE = "SAFE";
	 
	 FIFO18 FIFO_INST3(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout3), 
				.DOP(pout3), 
				.EMPTY(empty3), 
				.FULL(full3), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout2), 
				.DIP(pout2), 
				.RDCLK(clk), 
				.RDEN(en34), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en23)
				);
    defparam FIFO_INST3.DATA_WIDTH = 18;
    defparam FIFO_INST3.FIRST_WORD_FALL_THROUGH = "TRUE";
	 
	 FIFO18 FIFO_INST4(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout4), 
				.DOP(pout4), 
				.EMPTY(empty4), 
				.FULL(full4), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout3), 
				.DIP(pout3), 
				.RDCLK(clk), 
				.RDEN(en45), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en34)
				);
    defparam FIFO_INST4.DATA_WIDTH = 18;
    defparam FIFO_INST4.FIRST_WORD_FALL_THROUGH = "TRUE";
	 
	 FIFO18 FIFO_INST5(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout5), 
				.DOP(pout5), 
				.EMPTY(empty5), 
				.FULL(full5), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout4), 
				.DIP(pout4), 
				.RDCLK(clk), 
				.RDEN(en56), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en45)
				);
    defparam FIFO_INST5.DATA_WIDTH = 18;
    defparam FIFO_INST5.FIRST_WORD_FALL_THROUGH = "TRUE";
	 
	 FIFO18 FIFO_INST6(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout6), 
				.DOP(pout6), 
				.EMPTY(empty6), 
				.FULL(full6), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout5), 
				.DIP(pout5), 
				.RDCLK(clk), 
				.RDEN(en67), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en56)
				);
    defparam FIFO_INST6.DATA_WIDTH = 18;
    defparam FIFO_INST6.FIRST_WORD_FALL_THROUGH = "TRUE";
	 
	 FIFO18 FIFO_INST7(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(), 
				.DO(dataout7), 
				.DOP(pout7), 
				.EMPTY(empty7), 
				.FULL(full7), 
				.RDCOUNT(), 
				.RDERR(), 
		      .WRCOUNT(), 
				.WRERR(),
				//input
	         .DI(dataout6), 
				.DIP(pout6), 
				.RDCLK(clk), 
				.RDEN(en78), 
				.RST(rst), 
				.WRCLK(clk), 
				.WREN(en67)
				);
    defparam FIFO_INST7.DATA_WIDTH = 18;
    defparam FIFO_INST7.FIRST_WORD_FALL_THROUGH = "TRUE";
	 
	 FIFO18 FIFO_INST8(
            //output
				.ALMOSTEMPTY(), 
				.ALMOSTFULL(),