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/*
FreeRTOS.org V5.0.4 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution.
FreeRTOS.org is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS.org is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS.org; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS.org, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
***************************************************************************
* *
* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
* and even write all or part of your application on your behalf. *
* See http://www.OpenRTOS.com for details of the services we provide to *
* expedite your project. *
* *
***************************************************************************
***************************************************************************
Please ensure to read the configuration and relevant port sections of the
online documentation.
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/*
Changes from V2.4.2
+ The vErrorChecks() task now dynamically creates then deletes a task each
cycle. This tests the operation of the memory allocator.
Changes from V2.5.2
+ vParTestInitialise() is called during initialisation to ensure all the
LED's start off.
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "type.h"
#include "comtest2.h"
#include "uart.h"
#include "./app/kbd.h"
#include "./app/package.h"
#include "./app/keyscan.h"
#include "./lcd/lcddrive.h"
#include "./gui/GUI_StockC.h"
#include "./gui/font5_7.h"
/* Demo application includes.
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
*/
/*****************************************************************************
* Defines and typedefs
in mkd board , sdram is placeed in :
DYCS0 0xA000 0000 - 0xAFFF FFFF Dynamic 256 MB
total 32m bits ,or 16m words
bus wide : 16bits
****************************************************************************/
#define SDRAM_BASE_ADDR 0xA0000000
#define SDRAM_SIZE 0x02000000
#define LCD_FS 0x00000010 //P0.4
#define TICK_INC_RATE 10 //10 ms
/*-----------------------------------------------------------*/
/* Constants to setup I/O. */
#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0010 )
#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0040 )
#define mainP0_14 ( ( unsigned portLONG ) 0x4000 )
#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL )
/* Constants to setup the PLL. */
#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )
#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )
#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )
#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )
#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )
#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )
#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )
/* Constants to setup the MAM. */
#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )
#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )
/* Constants to setup the peripheral bus. */
#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* Priorities for the demo application tasks. */
#define mainMKD_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainKBD_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainPCK_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainTINC_TASK_PRIORITY ( tskIDLE_PRIORITY + 7 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 0 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 0 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which the on board LED will toggle when there is/is not an
error. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
/*-----------------------------------------------------------*/
void vStartPCKTasks( unsigned portBASE_TYPE uxPriority );
/*
* The Olimex demo board has a single built in LED. This function simply
* toggles its state.
*/
void prvToggleOnBoardLED( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*
* Configure the processor for use with the Olimex demo board. This includes
* setup for the I/O, system clock, and access timings.
*/
static void prvSetupHardware( void );
/*
* Initialize the SDRAM
*
*/
void SDRAMInit( void );
/*
* delayMs
*
*/
void delayMs( DWORD delay );
/*
* Initialize InitEMC
*
*/
void InitEMC(void);
/*-----------------------------------------------------------*/
//extern void vStartMKDTasks( unsigned portBASE_TYPE uxPriority );
//extern void vStartKBDTasks( unsigned portBASE_TYPE uxPriority );
//extern void GUI_Initialize(void);
//extern void (unsigned char ,unsigned char);
//extern void GUI_PutString(unsigned int , unsigned int y, char *);
extern void * xSerialPortInitMKD( unsigned portLONG ulWantedBaud);
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters );
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
unsigned portLONG ulMemCheckTaskRunningCount;
xTaskHandle xCreatedTask;
/* The parameters are not used in this function. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
In addition to the standard tests the memory allocator is tested through
the dynamic creation and deletion of a task each cycle. Each time the
task is created memory must be allocated for its stack. When the task is
deleted this memory is returned to the heap. If the task cannot be created
then it is likely that the memory allocation failed. */
for( ;; )
{
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
xCreatedTask = mainNO_TASK;
if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
//prvToggleOnBoardLED();
}
}
/*-----------------------------------------------------------*/
#define USE_USB 1
/* These are limited number of Fcco configuration for
USB communication as the CPU clock and USB clock shares
the same PLL. The USB clock needs to be multiple of
48Mhz. */
#if USE_USB /* 1 is USB, 0 is non-USB related */
/* Fcck = 48Mhz, Fosc = 288Mhz, and USB 48Mhz */
#define PLL_MValue 11
#define PLL_NValue 0
#define CCLKDivValue 5
#define USBCLKDivValue 5
/* System configuration: Fosc, Fcclk, Fcco, Fpclk must be defined */
/* PLL input Crystal frequence range 4KHz~20MHz. */
#define Fosc 12000000
/* System frequence,should be less than 80MHz. */
#define Fcclk 48000000
#define Fcco 288000000
#else
/* Fcck = 60Mhz, Fosc = 360Mhz, USB can't be divided into 48Mhz
in this case, so USBCLKDivValue is not needed. */
#define PLL_MValue 14
#define PLL_NValue 0
#define CCLKDivValue 5
/* System configuration: Fosc, Fcclk, Fcco, Fpclk must be defined */
/* PLL input Crystal frequence range 4KHz~20MHz. */
#define Fosc 12000000
/* System frequence,should be less than 72MHz. */
#define Fcclk 60000000
#define Fcco 360000000
#endif
/* APB clock frequence , must be 1/2/4 multiples of ( Fcclk/4 ). */
/* If USB is enabled, the minimum APB must be greater than 16Mhz */
#if USE_USB
#define Fpclk (Fcclk / 2)
#else
#define Fpclk (Fcclk / 4)
#endif
void xConfigurePLL ( void );
/******************************************************************************
** Function name: mdelay
**
** Descriptions:
**
** parameters: delay length
** Returned value: None
**
******************************************************************************/
void delayMs( DWORD delay )
{
DWORD i,j;
for( i = 0; i < delay * 40; i++)
for(j=0;j<1000;j++);
return;
}
/*****************************************************************************
** Function name: SDRAMInit
**
** Descriptions: Initialize external SDRAM memory Samsung
** K4S561632H, 256Mbit(4M x4 16 bit). The same
** code can be used for the Micron's MT48LC16M
** For more info. regarding the details of the
** SDRAMs, go to their website for data sheet.
**
** parameters: None
**
** Returned value: None
**
*****************************************************************************/
void SDRAMInit( void )
{
int i, dummy = dummy;
/*************************************************************************
* Initialize EMC and SDRAM
*************************************************************************/
// SCS |= 0x00000002; /* Reset EMC */
EMC_CTRL = 0x00000001; /*Disable Address mirror*/
PCONP |= 0x00000800; /* Turn On EMC PCLK */
PINSEL4 = 0x50000000;
PINSEL5 = 0x05050555;
PINSEL6 = 0x55555555;
PINSEL8 = 0x55555555;
PINSEL9 = 0x50555555;
EMC_DYN_RP = 2; /* command period: 3(n+1) clock cycles */
EMC_DYN_RAS = 3; /* RAS command period: 4(n+1) clock cycles */
EMC_DYN_SREX = 7; /* Self-refresh period: 8(n+1) clock cycles */
EMC_DYN_APR = 2; /* Data out to active: 3(n+1) clock cycles */
EMC_DYN_DAL = 5; /* Data in to active: 5(n+1) clock cycles */
EMC_DYN_WR = 1; /* Write recovery: 2(n+1) clock cycles */
EMC_DYN_RC = 5; /* Active to Active cmd: 6(n+1) clock cycles */
EMC_DYN_RFC = 5; /* Auto-refresh: 6(n+1) clock cycles */
EMC_DYN_XSR = 7; /* Exit self-refresh: 8(n+1) clock cycles */
EMC_DYN_RRD = 1; /* Active bank A->B: 2(n+1) clock cycles */
EMC_DYN_MRD = 2; /* Load Mode to Active cmd: 3(n+1) clock cycles */
EMC_DYN_RD_CFG = 1; /* Command delayed strategy */
/* Default setting, RAS latency 3 CCLKs, CAS latenty 3 CCLKs. */
EMC_DYN_RASCAS0 = 0x00000303;
/* 256MB, 16Mx16, 4 banks, row=13, column=9 */
EMC_DYN_CFG0 = 0x00000680; //should is this ,in mkd board
delayMs(1); /* use timer 1 */
/* Mem clock enable, CLKOUT runs, send command: NOP */
EMC_DYN_CTRL = 0x00000183;
delayMs(1); /* use timer 1 */
/* Send command: PRECHARGE-ALL, shortest possible refresh period */
EMC_DYN_CTRL = 0x00000103;
/* set 32 CCLKs between SDRAM refresh cycles */
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