100vhdl+

100vhdl例子

			-- exchange INT_S to bit_vector
			S := int_to_bit(INT_S, 9);

			-- output
			OFL <= S(8);
		elsif INT_A >= INT_B then		-- Substractor
			-- A - B
			INT_S := INT_A - INT_B;

			-- exchange INT_S to bit_vector
			S := int_to_bit(INT_S, 9);

			-- output
			OFL <= '0';
		else
			-- B - A
			INT_S := INT_B - INT_A;

			-- exchange INT_S to bit_vector
			S := int_to_bit(INT_S, 9);

			-- output
			OFL <= '1';
		end if;

		-- output
		S0 <= S(0);
		S1 <= S(1);
		S2 <= S(2);
		S3 <= S(3);
		S4 <= S(4);
		S5 <= S(5);
		S6 <= S(6);
		S7 <= S(7);
	end process;
end FUNC;

--------------------------------------------------
-- ADSU16H: 
--		16-Bit Adder/Substractor with Overflow and 
--	Fast-Carry Logic
--------------------------------------------------
use work.types.all;
entity ADSU16H is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	ADD: in  bit;
	OFL: out bit;
	S0 : out bit;
	S1 : out bit;
	S2 : out bit;
	S3 : out bit;
	S4 : out bit;
	S5 : out bit;
	S6 : out bit;
	S7 : out bit;
	S8 : out bit;
	S9 : out bit;
	S10: out bit;
	S11: out bit;
	S12: out bit;
	S13: out bit;
	S14: out bit;
	S15: out bit);
end ADSU16H;  

architecture FUNC of ADSU16H is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10, A11,A12,A13,A14,A15,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10, B11,B12,B13,B14,B15,ADD)
		variable A, B: bit_vector(15 downto 0);
		variable S: bit_vector(16 downto 0);
		variable INT_A, INT_B, INT_S: integer;
	begin
		-- initial
		A := A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		if ADD = '1' then			-- Adder 
			-- A + B
			INT_S := INT_A + INT_B;

			-- exchange INT_S to bit_vector
			S := int_to_bit(INT_S, 17);

			-- output
			OFL <= S(16);
		elsif INT_A >= INT_B then	-- Substractor
			-- A - B
			INT_S := INT_A - INT_B;

			-- exchange INT_S to bit_vector
			S := int_to_bit(INT_S, 17);

			-- output
			OFL <= '0';
		else
			-- B - A
			INT_S := INT_B - INT_A;

			-- exchange INT_S to bit_vector
			S := int_to_bit(INT_S, 17);

			-- output
			OFL <= '1';
		end if;

		-- output
		S0 <= S(0);
		S1 <= S(1);
		S2 <= S(2);
		S3 <= S(3);
		S4 <= S(4);
		S5 <= S(5);
		S6 <= S(6);
		S7 <= S(7);
		S8 <= S(7);
		S9 <= S(7);
		S10<= S(7);
		S11<= S(7);
		S12<= S(7);
		S13<= S(7);
		S14<= S(7);
		S15<= S(7);
	end process;
end FUNC;

---------------------------------------------------
-- MUL1: 
--		1-Bit Multipliers with Function Selection
---------------------------------------------------
use work.types.all;
entity MUL1 is port( 
	A : in  bit;
	B : in  bit;
	X : in  bit;
	Y : in  bit;
	P : out bit);
end MUL1;  

architecture FUNC of MUL1 is
begin
	P <= A and B;
end FUNC; 

---------------------------------------------------
-- MUL2: 
--		2-Bit Multipliers with Function Selection
---------------------------------------------------
use work.types.all;
entity MUL2 is port( 
	A0 : in  bit;
	A1 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	X  : in  bit;
	Y  : in  bit;
	P0 : out bit;
	P1 : out bit);
end MUL2;  

architecture FUNC of MUL2 is
begin
	process(A0, A1, B0, B1)
		variable A, B: bit_vector(1 downto 0);
		variable P: bit_vector(1 downto 0);
		variable INT_A, INT_B, INT_P: nat4;
	begin
		-- initial
		A := A1 & A0;
		B := B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- A * B
		INT_P := INT_A * INT_B;

		-- exchange INT_P to bit_vector
		P := int_to_bit(INT_P, 4);

		-- output
		P0 <= P(0);
		P1 <= P(1);
	end process;
end FUNC; 

---------------------------------------------------
-- MUL4: 
--		4-Bit Multipliers with Function Selection
---------------------------------------------------
use work.types.all;
entity MUL4 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	X  : in  bit;
	Y  : in  bit;
	P0 : out bit;
	P1 : out bit;
	P2 : out bit;
	P3 : out bit);
end MUL4;  

architecture FUNC of MUL4 is
begin
	process(A0, A1, A2, A3, B0, B1, B2, B3)
		variable A, B: bit_vector(3 downto 0);
		variable P: bit_vector(3 downto 0);
		variable INT_A, INT_B: nat4;
		variable INT_P: nat8;
	begin
		-- initial
		A := A3 & A2 & A1 & A0;
		B := B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- A * B
		INT_P := INT_A * INT_B;

		-- exchange INT_P to bit_vector
		P := int_to_bit(INT_P, 4);

		-- output
		P0 <= P(0);
		P1 <= P(1);
		P2 <= P(2);
		P3 <= P(3);
	end process;
end FUNC; 


---------------------------------------------------
-- MUL8: 
--		8-Bit Multipliers with Function Selection
---------------------------------------------------
use work.types.all;
entity MUL8 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	X  : in  bit;
	Y  : in  bit;
	P0 : out bit;
	P1 : out bit;
	P2 : out bit;
	P3 : out bit;
	P4 : out bit;
	P5 : out bit;
	P6 : out bit;
	P7 : out bit);
end MUL8;  

architecture FUNC of MUL8 is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7, B0,B1,B2,B3,B4,B5,B6,B7,X,Y)
		variable A, B: bit_vector(7 downto 0);
		variable P: bit_vector(7 downto 0);
		variable INT_A, INT_B: nat8;
		variable INT_P: nat16;
	begin
		-- initial
		A := A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- A * B
		INT_P := INT_A * INT_B;

		-- exchange INT_P to bit_vector
		P := int_to_bit(INT_P, 8);

		-- output
		P0 <= P(0);
		P1 <= P(1);
		P2 <= P(2);
		P3 <= P(3);
		P4 <= P(4);
		P5 <= P(5);
		P6 <= P(6);
		P7 <= P(7);
	end process;
end FUNC;

---------------------------------------------------
-- MUL16: 
--		16-Bit Multipliers with Function Selection
---------------------------------------------------
use work.types.all;
entity MUL16 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	X  : in  bit;
	Y  : in  bit;
	P0 : out bit;
	P1 : out bit;
	P2 : out bit;
	P3 : out bit;
	P4 : out bit;
	P5 : out bit;
	P6 : out bit;
	P7 : out bit;
	P8 : out bit;
	P9 : out bit;
	P10: out bit;
	P11: out bit;
	P12: out bit;
	P13: out bit;
	P14: out bit;
	P15: out bit);
end MUL16;  

architecture FUNC of MUL16 is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10, A11,A12,A13,A14,A15,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10, B11,B12,B13,B14,B15,X,Y)
		variable A, B: bit_vector(15 downto 0);
		variable P: bit_vector(15 downto 0);
		variable INT_A, INT_B: nat16;
		variable INT_P: integer;
	begin
		-- initial
		A := A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- A * B
		INT_P := INT_A * INT_B;

		-- exchange INT_P to bit_vector
		P := int_to_bit(INT_P, 16);

		-- output
		P0 <= P(0);
		P1 <= P(1);
		P2 <= P(2);
		P3 <= P(3);
		P4 <= P(4);
		P5 <= P(5);
		P6 <= P(6);
		P7 <= P(7);
		P8 <= P(8);
		P9 <= P(9);
		P10<= P(10);
		P11<= P(11);
		P12<= P(12);
		P13<= P(13);
		P14<= P(14);
		P15<= P(15);
	end process;
end FUNC;

---------------------------------------------------
-- MUL32: 
--		32-Bit Multipliers with Function Selection
---------------------------------------------------
use work.types.all;
entity MUL32 is port( 
	A0 : in  bit;
	A1 : in  bit;
	A2 : in  bit;
	A3 : in  bit;
	A4 : in  bit;
	A5 : in  bit;
	A6 : in  bit;
	A7 : in  bit;
	A8 : in  bit;
	A9 : in  bit;
	A10: in  bit;
	A11: in  bit;
	A12: in  bit;
	A13: in  bit;
	A14: in  bit;
	A15: in  bit;
	A16: in  bit;
	A17: in  bit;
	A18: in  bit;
	A19: in  bit;
	A20: in  bit;
	A21: in  bit;
	A22: in  bit;
	A23: in  bit;
	A24: in  bit;
	A25: in  bit;
	A26: in  bit;
	A27: in  bit;
	A28: in  bit;
	A29: in  bit;
	A30: in  bit;
	A31: in  bit;
	B0 : in  bit;
	B1 : in  bit;
	B2 : in  bit;
	B3 : in  bit;
	B4 : in  bit;
	B5 : in  bit;
	B6 : in  bit;
	B7 : in  bit;
	B8 : in  bit;
	B9 : in  bit;
	B10: in  bit;
	B11: in  bit;
	B12: in  bit;
	B13: in  bit;
	B14: in  bit;
	B15: in  bit;
	B16: in  bit;
	B17: in  bit;
	B18: in  bit;
	B19: in  bit;
	B20: in  bit;
	B21: in  bit;
	B22: in  bit;
	B23: in  bit;
	B24: in  bit;
	B25: in  bit;
	B26: in  bit;
	B27: in  bit;
	B28: in  bit;
	B29: in  bit;
	B30: in  bit;
	B31: in  bit;
	X  : in  bit;
	Y  : in  bit;
	P0 : out bit;
	P1 : out bit;
	P2 : out bit;
	P3 : out bit;
	P4 : out bit;
	P5 : out bit;
	P6 : out bit;
	P7 : out bit;
	P8 : out bit;
	P9 : out bit;
	P10: out bit;
	P11: out bit;
	P12: out bit;
	P13: out bit;
	P14: out bit;
	P15: out bit;
	P16: out bit;
	P17: out bit;
	P18: out bit;
	P19: out bit;
	P20: out bit;
	P21: out bit;
	P22: out bit;
	P23: out bit;
	P24: out bit;
	P25: out bit;
	P26: out bit;
	P27: out bit;
	P28: out bit;
	P29: out bit;
	P30: out bit;
	P31: out bit);
end MUL32;  

architecture FUNC of MUL32 is
begin
	process(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,
		    A11,A12,A13,A14,A15,A16,A17,A18,A19,A20,
	        A21,A22,A23,A24,A25,A25,A27,A28,A29,A30, A31,
	        B0,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,
		    B11,B12,B13,B14,B15,B16,B17,B18,B19,B20,
	        B21,B22,B23,B24,B25,B25,B27,B28,B29,B30, B31,X,Y)
		variable A, B: bit_vector(31 downto 0);
		variable P: bit_vector(31 downto 0);
		variable INT_A, INT_B, INT_P: integer;
	begin
		-- initial
		A := A31 & A30 & A29 & A28 & A27 & A26 & A25 & A24 & A23 & A22 & A21 & A20 & A19 & A18 & A17 & A16 & A15 & A14 & A13 & A12 & A11 & A10 & A9 & A8 & A7 & A6 & A5 & A4 & A3 & A2 & A1 & A0;
		B := B31 & B30 & B29 & B28 & B27 & B26 & B25 & B24 & B23 & B22 & B21 & B20 & B19 & B18 & B17 & B16 & B15 & B14 & B13 & B12 & B11 & B10 & B9 & B8 & B7 & B6 & B5 & B4 & B3 & B2 & B1 & B0;

		-- exchange A, B to integer
		INT_A := bit_to_int(A);
		INT_B := bit_to_int(B);

		-- A * B
		INT_P := INT_A * INT_B;

		-- exchange INT_P to bit_vector
		P := int_to_bit(INT_P, 32);

		-- output
		P0 <= P(0);
		P1 <= P(1);
		P2 <= P(2);
		P3 <= P(3);
		P4 <= P(4);
		P5 <= P(5);
		P6 <= P(6);
		P7 <= P(7);
		P8 <= P(8);
		P9 <= P(9);
		P10<= P(10);
		P11<= P(11);
		P12<= P(12);
		P13<= P(13);
		P14<= P(14);
		P15<= P(15);
		P16<= P(16);
		P17<= P(17);
		P18<= P(18);
		P19<= P(19);
		P20<= P(20);
		P21<= P(21);
		P22<= P(22);
		P23<= P(23);
		P24<= P(24);
		P25<= P(25);
		P26<= P(26);
		P27<= P(27);
		P28<= P(28);
		P29<= P(29);
		P30<= P(30);
		P31<= P(31);
	end process;
end FUNC;

--------------------------------------------------
-- The vhdl description for Xilinx Library (4000)
-- 
-- Category: Comparators 
--
-- Yan.Zongfu
-- 1995.10.17
--------------------------------------------------

------------------------------------
-- COMP2: 
--		2-Bit Identity Comparator
------------------------------------
use work.types.all;
entity COMP2 is port( 
		A0 : in  bit;
		A1 : in  bit;
		B0 : in  bit;
		B1 : in  bit;
		EQ : out bit);
end COMP2;

architecture FUNC of COMP2 is
begin
   process(A0,A1,B0,B1)
   begin
	  if (A0 = B0 and A1 = B1) then
		 EQ <= '1';
	  else
		 EQ <= '0';
      end if;
   end process;
end FUNC;