sd.c

u盘MCU端源代码,开发U盘的可以参考.

  {
    if (_mcu_register_rd(x_fmc_err) & kbm_fmc_err_sd_blk_ovrun)
    {
      //stop the current transfer
      sd_stop_transfer();
      n_bytes.u8.hi = _mcu_register_rd(x_fmc_cnt3);
      n_bytes.u8.lh = _mcu_register_rd(x_fmc_cnt2);
      n_bytes.u8.hl = _mcu_register_rd(x_fmc_cnt1);
      n_bytes.u8.lo = _mcu_register_rd(x_fmc_cnt0);
      trace4(0, sd, 0, "fmc_cnt#: %02x%02x%02x%02x", x_fmc_cnt3, x_fmc_cnt2, x_fmc_cnt1, x_fmc_cnt0);
      //No. of bytes sent to the host
      n_bytes.u32 = _current_byte_count.u32 - n_bytes.u32;
      //New LBA for the retry
      _fmc_set_start_lb_32(_fmc_get_start_lb_32() + (n_bytes.u32 / 512L)); 
      trace4(0, sd, 0, "read lba:%04X%04X xfer_length:%04X%04X", _hw(_fmc_get_start_lb_32()), _lw(_fmc_get_start_lb_32()), _hw(g_n_lb_this_xfer.u32), _lw(g_n_lb_this_xfer.u32));
      //clear and unmask the sd_blk_ovrrun interrupt so that we will be warned if this occurs
      irq_control(k_irq_fmc_err_sd_blk_ovrun, kbm_irqctl_clear);
      irq_control(k_irq_fmc_err, kbm_irqctl_unmask);
      //Check to see if the last two packets have gone out the door
      trace4(0, sd, 0, "bufferstat - ramrd_b:%d ramrd_a:%d ramwr_b:%d ramwr_a:%d", (_mcu_register_rd(x_isr0) & kbm_isr0_ramrd_b) ? 1 : 0, (_mcu_register_rd(x_isr0) & kbm_isr0_ramrd_a) ? 1 : 0, (_mcu_register_rd(x_isr0) & kbm_isr0_ramwr_b) ? 1 : 0, (_mcu_register_rd(x_isr0) & kbm_isr0_ramwr_a) ? 1 : 0);
      Result = sdc_wait_irq_with_timeout((kbm_isr0_ramrd_a |kbm_isr0_ramrd_b), 2000);
      if(Result != k_success)
        return Result;
      trace4(0, sd, 0, "bufferstat - ramrd_b:%d ramrd_a:%d ramwr_b:%d ramwr_a:%d", (_mcu_register_rd(x_isr0) & kbm_isr0_ramrd_b) ? 1 : 0, (_mcu_register_rd(x_isr0) & kbm_isr0_ramrd_a) ? 1 : 0, (_mcu_register_rd(x_isr0) & kbm_isr0_ramwr_b) ? 1 : 0, (_mcu_register_rd(x_isr0) & kbm_isr0_ramwr_a) ? 1 : 0);
      return (k_resume);
    }
    return (k_success);
  }
  for(n=0; n<8;n++)
  {
    _mcu_begin_critical_section();
    //Point to buffer A
#ifdef k_dbg_on
    dbg_dumpram(_l(addr_word),_h(addr_word), FS_pktsz);
#endif
    _mcu_register_wr(x_sram_addr_lo, k_pkt_addrlo[4] + _l(offset));
    _mcu_register_wr(x_sram_addr_hi, k_pkt_addrhi[4] + _h(offset));
    _nop_();
    _sd_copy_buf_to_xdata();
    //Point to buffer B
    _mcu_register_wr(x_sram_addr_lo, k_pkt_addrlo[5]);
    _mcu_register_wr(x_sram_addr_hi, k_pkt_addrhi[5]);
    _nop_();
    _sd_copy_xdata_to_buf();
    //see what we have copied
#ifdef k_dbg_on
    dbg_dumpram(_l(addr_word),_h(addr_word), FS_pktsz);
#endif


    //tell how many bytes to xmit
    _mcu_register_wr(x_ramrdbc_b2, FS_pktsz);
    _mcu_register_wr(x_ramrdbc_b1, FS_pktsz);
    //transmit the packet
    _mcu_register_clr_bits(x_ep2_ctl, kbm_ep2_ctl_wrtog_valid);
    // aim/set ramrd_tog at buffer B so it is ARMED for tx (clrs isr0 ramrd_b bit also)
    _mcu_register_set_bits(x_ep2_ctl, kbm_ep2_ctl_rdtog_valid |kbm_ep2_ctl_ramrd_tog);
    // _mcu_register_wr(x_isr0, kbm_isr0_ramrd_b);
    _nop_();_nop_();_nop_();_nop_();_nop_();
    _mcu_end_critical_section();
#ifdef sd_fast_1point1
    while(!(_mcu_register_rd(x_isr0) & kbm_isr0_ramrd_b));
#else
    Result = sdc_wait_irq_with_timeout(kbm_isr0_ramrd_b, 2000);
    if(Result != k_success)
      return Result;
#endif
    offset = offset + FS_pktsz;
  }
#ifdef k_dbg_on
  dbg_bufferstat();
#endif
  return k_success;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void dfa_sd_read() reentrant
{
  g_cdm0 = 0;
  trace1(0, tm, 0, "@%d Start sd_read", g_cdm0);
  trace0(0, sd, 3, "+sd_read()");
  //Jump to this location on an "Emergency Exit" due to sync_abort or sync_usbreset
  if(setjmp(_sd_context))
    __thread_return_dfa(k_command_failed);
  //clear and unmask the sd_blk_ovrrun interrupt so that we will be warned if this occurs
  irq_control(k_irq_fmc_err_sd_blk_ovrun, kbm_irqctl_clear);
  irq_control(k_irq_fmc_err, kbm_irqctl_unmask);
  if(sie_is_high_speed())
  {
    trace0(0, sd, 3, "Doing High Speed!");
    _sd_data_xfer_cmd = k_sdc_cmd_read_mult_blocks;
    //set the callbacks
    //_fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,sd_read_write_begin_split, fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback);
    _fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,fmc_dflt_callback, fmc_dflt_callback,fmc_dflt_callback,sd_read_intra_burst,sd_read_end_burst);
  } else
  {
    trace0(0, sd, 3, "Doing Full Speed!");
    _sd_data_xfer_cmd = k_sdc_cmd_read_sgl_block;
    //set the callbacks
    _fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback,sd_read_intra_burst,sd_read_end_burst);
  }
  // 04/28/02 tbh/ds - xdata is not initialized to zero on power up.
  // do not depend on the fmc options being cleared to zero at power on.
  _fmc_set_options(0);
  dfa_lun_read();
  trace1(0, tm, 0, "@%d End sd_read", g_cdm0);
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
t_result sd_write_copy_data() reentrant;
t_result sd_write_copy_data() reentrant
{
  //allocate 64 bytes of xdata space for the temporary holder
  uint8  n, Result = 0;
  uint16 offset = 0;
  g_cdm0 = 0;
  trace1(0, sd, 0, "@%d Start write copy data", g_cdm0);
  mmu_deallocate(5);              // ready to get the next set of data
  //mmu_deallocate(4);
  _mcu_register_wr(x_isr0, kbm_isr0_ramwr_a);
  //_buffer_rx_enable(4);
  _mcu_register_wr(x_ep2_ctl, (_mcu_register_rd(x_ep2_ctl) & ~kbm_ep2_ctl_ramwr_tog) |kbm_ep2_ctl_wrtog_valid);
  for(n=0; n<8;n++)
  {
    //get the buffer ready to receive data
#ifdef k_dbg_on
    dbg_bufferstat();
#endif
#ifdef sd_fast_1point1
    thread_set_timer(2000);
    while(!thread_got_sync(kbm_sync_usbrx))
    {
      if(thread_got_sync(kbm_sync_timer))
      {
        return k_timeout;
      }
    }
    thread_clr_sync(kbm_sync_usbrx);
#else
    Result = sdc_wait_irq_with_timeout(kbm_isr0_ramwr_a, 2000);
    if(Result != k_success)
      return Result;
#endif


    //Start the copying process
    trace1(0, tm, 0, "@%d Start copy", g_cdm0);
    mcu_begin_critical_section();
    //Point to buffer A
#ifdef k_dbg_on
    dbg_dumpram(k_pkt_addrlo[4],k_pkt_addrhi[4], FS_pktsz);
#endif
    _mcu_register_wr(x_sram_addr_lo, k_pkt_addrlo[4]);
    _mcu_register_wr(x_sram_addr_hi,k_pkt_addrhi[4]);
    _nop_();
    _sd_copy_buf_to_xdata();
    //let the next pkt come in
    if(n != 7)
    {
      //mmu_deallocate(4);
      _mcu_register_wr(x_isr0, kbm_isr0_ramwr_a);
      //_buffer_rx_enable(4);
      _mcu_register_wr(x_ep2_ctl, (_mcu_register_rd(x_ep2_ctl) & ~kbm_ep2_ctl_ramwr_tog) |kbm_ep2_ctl_wrtog_valid);
    }
    //Point to buffer B
    _mcu_register_wr(x_sram_addr_lo, k_pkt_addrlo[5] + _l(offset));
    _mcu_register_wr(x_sram_addr_hi, k_pkt_addrhi[5] + _h(offset));
    _nop_();
    _sd_copy_xdata_to_buf();
    offset = offset + FS_pktsz;
    mcu_end_critical_section();
    trace1(0, tm, 0, "@%d End copy", g_cdm0);
    //see what we have copied
#ifdef k_dbg_on
    dbg_dumpram(_l(addr_word),_h(addr_word), FS_pktsz);
#endif
  }
  trace0(0, sd, 0, "Setting Data Loaded to true");
  _sd_data_loaded = k_true;
  return k_success;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
t_result sd_write_begin_burst() reentrant
{
  t_result Result = 0;
  trace0(0, sd, 3, "sd_write_begin_burst");
  if(_sd_data_loaded == k_false)
  {
    trace0(0, sd, 0, "Data Not Loaded yet..");
    Result = sd_write_copy_data();
  }
  //Now the 512 bytes from Buffer B needs to go to fmdu
  //get the buffer B ready to transmit data
#ifdef k_dbg_on
  dbg_bufferstat();
#endif
  mcu_begin_critical_section();
  thread_clr_sync(kbm_sync_usbtx);
  _mcu_register_wr(x_isr0, kbm_isr0_ramrd_b);
  _mcu_register_wr(x_ramrdbc_b2, _l(512));
  _mcu_register_wr(x_ramrdbc_b1, _h(512));
  // aim/set ramrd_tog at buffer B so it is ARMED for tx (clrs isr0 ramrd_b bit also)
  _mcu_register_set_bits(x_ep2_ctl, kbm_ep2_ctl_rdtog_valid |kbm_ep2_ctl_ramrd_tog);
#ifdef k_dbg_on
  dbg_bufferstat();
#endif


  // mask it back in to get the irq
  _mcu_register_clr_bits(x_imr0, kbm_isr0_ramrd_b);
  mcu_end_critical_section();
  _mcu_register_wr(x_sdc_stat, kbm_sdc_stat_crd_rdy);
  trace1(0, sd, 0, "@%d End write burst", g_cdm0);
  _sd_data_loaded = k_false;
  return k_success;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
t_result sd_write_end_burst() reentrant
{
  t_result Result;
  //if this is an aborted transfer get out immediately
  if(k_success != g_fmc_rslt)
  {
    trace2(0, sd, 3, "Aborted transfer ... getting out of here! %d  %d",g_fmc_rslt, _fmc_get_result());
    return _fmc_get_result();
  }
  trace1(0, sd, 1, "_sd_data_loaded : %02x",_sd_data_loaded);
  //The data has been sent to fmdu.
  if((_sd_data_loaded == k_false) && (_mscbot_residue_32() - (uint32)512))
  {
    trace0(0, sd, 0, "Data Not Loaded yet..");
    Result = sd_write_copy_data();
  }
  trace1(0, sd, 3, "The stat register %02x",_mcu_register_rd(x_sdc_stat));
  Result = fmc_wait_blk_irq_with_timeout(g_fmc_timeout);
  if(Result == k_success)
    if(!(x_sdc_stat & kbm_sdc_stat_crd_rdy))
      sdc_wait_status_with_timeout(kbm_sdc_stat_crd_rdy,1000);
  return Result;
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void dfa_sd_write(void) reentrant
{
  //t_result result;
  trace0(0, sd, 3, "+sd_write()");
  //Jump to this location on an "Emergency Exit" due to sync_abort or sync_usbreset
  if(setjmp(_sd_context))
  {
    trace0(0, sd, 0, "EMERGENCY EXIT!!");
    __thread_return_dfa(k_command_failed);
  }
  //Is the media write protected?
  /*if(_sd_write_protected)
  {
    _lun_data(sensep) = &sense_write_protect;
    __thread_return_dfa(k_command_failed)
  } */
  if(sie_is_high_speed())
  {
    trace0(0, sd, 3, "Doing High Speed!");
    _sd_data_xfer_cmd = k_sdc_cmd_write_mult_blocks;
    //set the callbacks
    _fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,sd_read_write_begin_split, fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback);
  } else
  {
    trace0(0, sd, 3, "Doing Full Speed!");
    _sd_data_xfer_cmd = k_sdc_cmd_write_mult_blocks;
    //set the callbacks
    _fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,sd_read_write_begin_split, fmc_dflt_callback,sd_write_begin_burst,fmc_dflt_callback, sd_write_end_burst);
  }
  // 04/28/02 tbh/ds - xdata is not initialized to zero on power up.
  // do not depend on the fmc options being cleared to zero at power on.
  _fmc_set_options(0);
  dfa_lun_write();
}

//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
void dfa_sd_verify(void) reentrant
{
  trace0(0, sd, 0, "+sd_verify()");
  //Jump to this location on an "Emergency Exit" due to sync_abort or sync_usbreset
  if(setjmp(_sd_context))
    thread_return_dfa(k_command_failed);
  if(sie_is_high_speed())
  {
    trace0(0, sd, 0, "Doing High Speed!");
    _sd_data_xfer_cmd = k_sdc_cmd_write_mult_blocks;
    //set the callbacks
    _fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,sd_read_write_begin_split, fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback,fmc_dflt_callback);
  } else
  {
    trace0(0, sd, 0, "Doing Full Speed!");
    _sd_data_xfer_cmd = k_sdc_cmd_write_mult_blocks;
    //set the callbacks
    _fmc_set_callback(sd_read_write_begin_xfer,sd_read_write_end_xfer,sd_read_write_begin_split, fmc_dflt_callback, sd_write_begin_burst,fmc_dflt_callback,sd_write_end_burst);
  }
  // 04/28/02 tbh/ds - xdata is not initialized to zero on power up.
  // do not depend on the fmc options being cleared to zero at power on.
  _fmc_set_options(0);
  dfa_lun_verify();
}

//---eof------------------------------------------------------------------------