📄 fifo_tb.v
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`timescale 1ns/100psmodule fifotb;reg clk;reg[7:0] din;reg rd_en;reg rst;reg wr_en;wire[7:0]dout;wire empty,full;fifo16 fifo16(clk, din, rd_en, rst, wr_en, dout, empty, full);parameter period=40;initial beginclk=0;rst=0;#periodrst=1;#periodrst=0;endalways #(period/2) clk=~clk;initial begindin=0;repeat (20)begin #period din=din+1; endendinitial beginrd_en=0;wr_en=0;#(5*period)wr_en=1;#(8*period)wr_en=0;#(2*period)rd_en=1;#(6*period)rd_en=0;#(10*period)$stop;endendmodule
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