fifo_tb.v

来自「Reed-Solomon 信道编码广泛应用于DVB中」· Verilog 代码 · 共 53 行

`timescale 1ns/100ps
module fifotb;
reg clk;
reg[7:0] din;
reg rd_en;
reg rst;
reg wr_en;
wire[7:0]dout;
wire empty,full;

fifo16 fifo16(clk,
	din,
	rd_en,
	rst,
	wr_en,
	dout,
	empty,
	full);
parameter period=40;

initial begin
clk=0;
rst=0;
#period
rst=1;
#period
rst=0;
end
always #(period/2) clk=~clk;
initial begin
din=0;
repeat (20)
begin
	#period din=din+1;
	end
end

initial begin
rd_en=0;
wr_en=0;
#(5*period)
wr_en=1;
#(8*period)
wr_en=0;
#(2*period)
rd_en=1;
#(6*period)
rd_en=0;
#(10*period)
$stop;
end

endmodule