fifo_generator_v2_0.v

Reed-Solomon 信道编码广泛应用于DVB中

			 //Acknowledge the read from the FIFO, no error
			 ideal_valid <= 1'b1; 
			 ideal_underflow <= 1'b0;
			 //Fifo is not yet empty. It is going almost_empty
			 ideal_empty  <= 1'b0;
			 ideal_almost_empty <= 1'b1;
			 
			 ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
			 
		      end // if (tmp_rd_listsize == 2)

		    //If the FIFO is one from empty
		    else if ((tmp_rd_listsize/C_RATIO_W == 1))
		      begin
			 //Read the value from the FIFO
			 read_fifo;
			 next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
			 
			 //Acknowledge the read from the FIFO, no error
			 ideal_valid <= 1'b1;
			 ideal_underflow <= 1'b0;
			 //Note that FIFO is GOING empty
			 ideal_empty  <= 1'b1; 
			 ideal_almost_empty <= 1'b1; 
			 
			 ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
			 
		      end // if (tmp_rd_listsize == 1)

		    
		    //If the FIFO is completely empty
		    else if (tmp_rd_listsize/C_RATIO_W <= 0)
		      begin
			 //Do not change the contents of the FIFO

			 //Do not acknowledge the read from empty FIFO
			 ideal_valid <= 1'b0;
			 //Throw an underflow error
			 ideal_underflow <= 1'b1;
			 //Reminder that FIFO is still empty
			 ideal_empty  <= 1'b1; 
			 ideal_almost_empty <= 1'b1;
			 
			 ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
			 
		      end // if (tmp_rd_listsize <= 0)
		    
		 end // if (ideal_empty == 1'b0)
	       
	    end //(RD_EN == 1'b1)
	    
	    else //if (RD_EN == 1'b0)
	      begin
		 //If user did not attempt a read, do not give an ack or err
		 ideal_valid <= 1'b0;
		 ideal_underflow <= 1'b0;
		 
		 //Check for empty
		 if (tmp_rd_listsize/C_RATIO_W <= 0)     
		   ideal_empty  <= 1'b1;
		 else
		   ideal_empty  <= 1'b0;
		 
		 //Check for almost_empty
		 if (tmp_rd_listsize/C_RATIO_W <= 1)      
		   ideal_almost_empty  <= 1'b1;
		 else
		   ideal_almost_empty  <= 1'b0;
		 
		 ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		 
	      end // else: !if(RD_EN == 1'b1)

	    /*****************************************************************/
	    // Read Operation - Read Latency 0
	    /*****************************************************************/
	 end else if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0) begin
	    if (RD_EN == 1'b1) begin
	       
	       if (ideal_empty == 1'b1) begin
		  
		  //If the FIFO is completely empty, and is reporting empty
		  if (tmp_rd_listsize/C_RATIO_W <= 0) begin
		     //Do not change the contents of the FIFO

		     //Do not acknowledge the read from empty FIFO
		     ideal_valid <= 1'b0;
		     //Throw an underflow error
		     ideal_underflow <= 1'b1;
		     //Reminder that FIFO is still empty
		     ideal_empty  <= 1'b1; 
		     ideal_almost_empty <= 1'b1;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		     //If the FIFO is one from empty, but it is reporting empty
		  end else if (tmp_rd_listsize/C_RATIO_W == 1) begin
		     //Do not change the contents of the FIFO

		     //Do not acknowledge the read from empty FIFO
		     ideal_valid <= 1'b0;
		     //Throw an underflow error
		     ideal_underflow <= 1'b1;
		     //Note that FIFO is no longer empty, but is almost empty (has one word left)
		     ideal_empty  <= 1'b0; 
		     ideal_almost_empty <= 1'b1; 
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		     //If the FIFO is two from empty, and is reporting empty
		  end else if (tmp_rd_listsize/C_RATIO_W == 2) begin
		     //Do not change the contents of the FIFO

		     //Do not acknowledge the read from empty FIFO
		     ideal_valid <= 1'b0;
		     //Throw an underflow error
		     ideal_underflow <= 1'b1;
		     //Fifo has two words, so is neither empty or almost empty
		     ideal_empty  <= 1'b0;
		     ideal_almost_empty <= 1'b0;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		     
		     //If the FIFO is not close to empty, but is reporting that it is
		     // Treat the FIFO as empty this time, but unset EMPTY flags.
		  end else if ((tmp_rd_listsize/C_RATIO_W > 2) && 
			       (tmp_rd_listsize/C_RATIO_W<C_FIFO_RD_DEPTH)) begin
		     //Do not change the contents of the FIFO

		     //Do not acknowledge the read from empty FIFO
		     ideal_valid <= 1'b0;
		     //Throw an underflow error
		     ideal_underflow <= 1'b1;
		     //Note that the FIFO is No Longer Empty or Almost Empty
		     ideal_empty  <= 1'b0; 
		     ideal_almost_empty <= 1'b0;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		  end // if ((tmp_rd_listsize > 2) && (tmp_rd_listsize<=C_FIFO_RD_DEPTH-1))

	       end else begin
		  
		  //If the FIFO is completely full, and we are successfully reading from it
		  if (tmp_rd_listsize/C_RATIO_W >= C_FIFO_RD_DEPTH) begin
		     //Read the value from the FIFO
		     read_fifo;
		     next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;

		     //Acknowledge the read from the FIFO, no error
		     ideal_valid <= 1'b1; 
		     ideal_underflow <= 1'b0;
		     //Not close to empty
		     ideal_empty  <= 1'b0;
		     ideal_almost_empty <= 1'b0;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		     //If the FIFO is not close to being empty
		  end else if ((tmp_rd_listsize/C_RATIO_W > 2) && 
			       (tmp_rd_listsize/C_RATIO_W<=C_FIFO_RD_DEPTH)) begin
		     //Read the value from the FIFO
		     read_fifo;
		     next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;

		     //Acknowledge the read from the FIFO, no error
		     ideal_valid <= 1'b1; 
		     ideal_underflow <= 1'b0;
		     //Not close to empty
		     ideal_empty  <= 1'b0;
		     ideal_almost_empty <= 1'b0;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     

		     //If the FIFO is two from empty
		  end else if (tmp_rd_listsize/C_RATIO_W == 2) begin
		     //Read the value from the FIFO
		     read_fifo;
		     next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
		     
		     //Acknowledge the read from the FIFO, no error
		     ideal_valid <= 1'b1; 
		     ideal_underflow <= 1'b0;
		     //Fifo is not yet empty. It is going almost_empty
		     ideal_empty  <= 1'b0;
		     ideal_almost_empty <= 1'b1;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		     //If the FIFO is one from empty
		  end else if (tmp_rd_listsize/C_RATIO_W == 1) begin
		     //Read the value from the FIFO
		     read_fifo;
		     next_num_rd_bits = next_num_rd_bits - C_DOUT_WIDTH;
		     
		     //Acknowledge the read from the FIFO, no error
		     ideal_valid <= 1'b1;
		     ideal_underflow <= 1'b0;
		     //Note that FIFO is GOING empty
		     ideal_empty  <= 1'b1; 
		     ideal_almost_empty <= 1'b1; 
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		     //If the FIFO is completely empty
		  end else if (tmp_rd_listsize/C_RATIO_W <= 0) begin
		     //Do not change the contents of the FIFO

		     //Do not acknowledge the read from empty FIFO
		     ideal_valid <= 1'b0;
		     //Throw an underflow error
		     ideal_underflow <= 1'b1;
		     //Reminder that FIFO is still empty
		     ideal_empty  <= 1'b1; 
		     ideal_almost_empty <= 1'b1;
		     
		     ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		     
		  end // if (tmp_rd_listsize <= 0)
		  
	       end // if (ideal_empty == 1'b0)
	       
	    end //(RD_EN == 1'b1)
	    
	    else //if (RD_EN == 1'b0)
	      begin
		 //If user did not attempt a read, do not give an ack or err
		 ideal_valid <= 1'b0;
		 ideal_underflow <= 1'b0;
		 
		 //Check for empty
		 if (tmp_rd_listsize/C_RATIO_W <= 0)     
		   ideal_empty  <= 1'b1;
		 else
		   ideal_empty  <= 1'b0;
		 
		 //Check for almost_empty
		 if (tmp_rd_listsize/C_RATIO_W <= 1)      
		   ideal_almost_empty  <= 1'b1;
		 else
		   ideal_almost_empty  <= 1'b0;
		 
		 ideal_rd_count <= num_read_words[C_RD_PNTR_WIDTH-1:C_RD_PNTR_WIDTH-C_RD_DATA_COUNT_WIDTH];
		 
	      end // else: !if(RD_EN == 1'b1)
	 end //if (C_PRELOAD_REGS==1 && C_PRELOAD_LATENCY==0)
	 

	 /*********************************************************
	  * Programmable EMPTY flags
	  *********************************************************/
	 //Single Programmable Empty Constant Threshold
	 if (C_PROG_EMPTY_TYPE==1) begin
	    if (RST) begin
	       prog_empty_d <= 1'b1;

	       // If we will be going at or below the 
	       // C_PROG_EMPTY_THRESH_ASSERT_VAL threshold on the next clock
	       // cycle, then assert PROG_EMPTY. There may be pending 
	       // writes that haven't caught up yet, but we need to assume the worst
	    end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) 
			 && RD_EN) begin
	       prog_empty_d <= 1'b1;

	       // If we are at or below the C_PROG_EMPTY_THRESH_ASSERT_VAL, 
	       // then assert PROG_EMPTY
	    end else if (num_read_words <= C_PROG_EMPTY_THRESH_ASSERT_VAL) begin
	       prog_empty_d <= 1'b1;

	       // If we are above the C_PROG_EMPTY_THRESH_NEGATE_VAL, then 
	       // de-assert PROG_EMPTY
	    end else if (num_read_words > C_PROG_EMPTY_THRESH_ASSERT_VAL) begin
	       prog_empty_d <= 1'b0;
	    end

	    //Two Programmable Empty Constant Thresholds
	 end else if (C_PROG_EMPTY_TYPE==2) begin
	    if (RST) begin
	       prog_empty_d <= 1'b1;
	       
	       // If we will be going at or below the 
	       // C_PROG_EMPTY_THRESH_ASSERT_VAL threshold on the next clock
	       // cycle, then assert PROG_EMPTY. There may be pending 
	       // writes that haven't caught up yet, but we need to assume the worst
	    end else if ((num_read_words == C_PROG_EMPTY_THRESH_ASSERT_VAL+1) 
			 && RD_EN) begin
	       prog_empty_d <= 1'b1;

	       // If we are at or below the C_PROG_EMPTY_THRESH_ASSERT_VAL, 
	       // then assert PROG_EMPTY
	    end else if (num_read_words <= C_PROG_EMPTY_THRESH_ASSERT_VAL) begin
	       prog_empty_d <= 1'b1;

	       // If we are above the C_PROG_EMPTY_THRESH_NEGATE_VAL, then 
	       // de-assert PROG_EMPTY
	    end else if (num_read_words > C_PROG_EMPTY_THRESH_NEGATE_VAL) begin
	       prog_empty_d <= 1'b0;
	    end

	    //Single Programmable Empty Constant Threshold
	 end else if (C_PROG_EMPTY_TYPE==3) begin
	    if (RST) begin
	       prog_empty_d <= 1'b1;
	       
	       // If we will be going at or below the 
	       // PROG_EMPTY_THRESH_ASSERT threshold on the next clock
	       // cycle, then assert PROG_EMPTY. There may be pending 
	       // writes that haven't caught up yet, but we need to assume the worst
	    end else if ((num_read_words == PROG_EMPTY_THRESH+1) 
			 && RD_EN) begin
	       prog_empty_d <= 1'b1;

	       // If we are at or below the PROG_EMPTY_THRESH_ASSERT, 
	       // then assert PROG_EMPTY
	    end else if (num_read_words <= PROG_EMPTY_THRESH) begin
	       prog_empty_d <= 1'b1;

	       // If we are above the PROG_EMPTY_THRESH_NEGATE, then 
	       // de-assert PROG_EMPTY
	    end else if (num_read_words > PROG_EMPTY_THRESH) begin
	       prog_empty_d <= 1'b0;
	    end

	    //Two Programmable Empty Constant Thresholds
	 end else if (C_PROG_EMPTY_TYPE==4) begin
	    if (RST) begin
	       prog_empty_d <= 1'b1;
	       
	       // If we will be going at or below the 
	       // PROG_EMPTY_THRESH_ASSERT threshold on the next clock
	       // cycle, then assert PROG_EMPTY. There may be pending 
	       // writes that haven't caught up yet, but we need to assume the worst
	    end else if ((num_read_words == PROG_EMPTY_THRESH_ASSERT+1) 
			 && RD_EN) begin
	       prog_empty_d <= 1'b1;

	       // If we are at or below the PROG_EMPTY_THRESH_ASSERT, 
	       // then assert PROG_EMPTY
	    end else if (num_read_words <= PROG_EMPTY_THRESH_ASSERT) begin
	       prog_empty_d <= 1'b1;

	       // If we are above the PROG_EMPTY_THRESH_NEGATE, then 
	       // de-assert PROG_EMPTY
	    end else if (num_read_words > PROG_EMPTY_THRESH_NEGATE) begin
	       prog_empty_d <= 1'b0;
	    end

	 end
	 

	 ideal_prog_empty <= prog_empty_d;  
	 ideal_rd_count_q <= ideal_rd_count;
	 num_rd_bits      <= next_num_rd_bits;
	 wr_ptr_rdclk_q   <= wr_ptr_rdclk;
	 wr_ptr_rdclk     <= wr_ptr;
      end
   end 

endmodule // fifo_generator_v2_0_bhv_ver_as



  


  
/*******************************************************************************
 * Declaration of top-level module
 ******************************************************************************/
module fifo_generator_v2_0_bhv_ver_ss
  (
    CLK, RST, DIN, WR_EN, RD_EN, 
    PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, 
    PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, 
    DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, 
    ALMOST_EMPTY, VALID, UNDERFLOW, DA