fifo_generator_v2_0.v

Reed-Solomon 信道编码广泛应用于DVB中

    C_COUNT_TYPE,
    C_DATA_COUNT_WIDTH,
    C_DEFAULT_VALUE,
    C_DIN_WIDTH,
    C_DOUT_RST_VAL,
    C_DOUT_WIDTH,
    C_ENABLE_RLOCS,
    C_FAMILY,//Not allowed in Verilog model
    C_HAS_ALMOST_EMPTY,
    C_HAS_ALMOST_FULL,
    C_HAS_BACKUP,
    C_HAS_DATA_COUNT,
    C_HAS_MEMINIT_FILE,
    C_HAS_OVERFLOW,
    C_HAS_RD_DATA_COUNT,
    C_HAS_RD_RST,
    C_HAS_RST,
    C_HAS_UNDERFLOW,
    C_HAS_VALID,
    C_HAS_WR_ACK,
    C_HAS_WR_DATA_COUNT,
    C_HAS_WR_RST,
    C_IMPLEMENTATION_TYPE,
    C_INIT_WR_PNTR_VAL,
    C_MEMORY_TYPE,
    C_MIF_FILE_NAME,
    C_OPTIMIZATION_MODE,
    C_OVERFLOW_LOW,
    C_PRELOAD_LATENCY,
    C_PRELOAD_REGS,
    C_PROG_EMPTY_THRESH_ASSERT_VAL,
    C_PROG_EMPTY_THRESH_NEGATE_VAL,
    C_PROG_EMPTY_TYPE,
    C_PROG_FULL_THRESH_ASSERT_VAL,
    C_PROG_FULL_THRESH_NEGATE_VAL,
    C_PROG_FULL_TYPE,
    C_RD_DATA_COUNT_WIDTH,
    C_RD_DEPTH,
    C_RD_PNTR_WIDTH,
    C_UNDERFLOW_LOW,
    C_VALID_LOW,
    C_WR_ACK_LOW,
    C_WR_DATA_COUNT_WIDTH,
    C_WR_DEPTH,
    C_WR_PNTR_WIDTH,
    C_WR_RESPONSE_LATENCY
  )
  gen_as
  (
    .WR_CLK(WR_CLK_1), 
    .RD_CLK(RD_CLK_1), 
    .RST(RST_1), 
    .DIN(DIN_1), 
    .WR_EN(WR_EN_1), 
    .RD_EN(RD_EN_1), 
    .PROG_EMPTY_THRESH(PROG_EMPTY_THRESH_1), 
    .PROG_EMPTY_THRESH_ASSERT(PROG_EMPTY_THRESH_ASSERT_1), 
    .PROG_EMPTY_THRESH_NEGATE(PROG_EMPTY_THRESH_NEGATE_1), 
    .PROG_FULL_THRESH(PROG_FULL_THRESH_1), 
    .PROG_FULL_THRESH_ASSERT(PROG_FULL_THRESH_ASSERT_1), 
    .PROG_FULL_THRESH_NEGATE(PROG_FULL_THRESH_NEGATE_1), 
    .DOUT(DOUT_I_1), 
    .FULL(FULL_I_1), 
    .ALMOST_FULL(ALMOST_FULL_I_1), 
    .WR_ACK(WR_ACK_I_1), 
    .OVERFLOW(OVERFLOW_I_1), 
    .EMPTY(EMPTY_I_1), 
    .ALMOST_EMPTY(ALMOST_EMPTY_I_1), 
    .VALID(VALID_I_1), 
    .UNDERFLOW(UNDERFLOW_I_1), 
    .RD_DATA_COUNT(RD_DATA_COUNT_I_1), 
    .WR_DATA_COUNT(WR_DATA_COUNT_I_1), 
    .PROG_FULL(PROG_FULL_I_1), 
    .PROG_EMPTY(PROG_EMPTY_I_1)
   );

 
  
fifo_generator_v2_0_bhv_ver_fifo16
  #(
    C_COMMON_CLOCK,
    C_COUNT_TYPE,
    C_DATA_COUNT_WIDTH,
    C_DEFAULT_VALUE,
    C_DIN_WIDTH,
    C_DOUT_RST_VAL,
    C_DOUT_WIDTH,
    C_ENABLE_RLOCS,
    C_FAMILY,//Not allowed in Verilog model
    C_HAS_ALMOST_EMPTY,
    C_HAS_ALMOST_FULL,
    C_HAS_BACKUP,
    C_HAS_DATA_COUNT,
    C_HAS_MEMINIT_FILE,
    C_HAS_OVERFLOW,
    C_HAS_RD_DATA_COUNT,
    C_HAS_RD_RST,
    C_HAS_RST,
    C_HAS_UNDERFLOW,
    C_HAS_VALID,
    C_HAS_WR_ACK,
    C_HAS_WR_DATA_COUNT,
    C_HAS_WR_RST,
    C_IMPLEMENTATION_TYPE,
    C_INIT_WR_PNTR_VAL,
    C_MEMORY_TYPE,
    C_MIF_FILE_NAME,
    C_OPTIMIZATION_MODE,
    C_OVERFLOW_LOW,
    C_PRELOAD_LATENCY,
    C_PRELOAD_REGS,
     C_PRIM_FIFO_TYPE,
    C_PROG_EMPTY_THRESH_ASSERT_VAL,
    C_PROG_EMPTY_THRESH_NEGATE_VAL,
    C_PROG_EMPTY_TYPE,
    C_PROG_FULL_THRESH_ASSERT_VAL,
    C_PROG_FULL_THRESH_NEGATE_VAL,
    C_PROG_FULL_TYPE,
    C_RD_DATA_COUNT_WIDTH,
    C_RD_DEPTH,
    C_RD_PNTR_WIDTH,
    C_UNDERFLOW_LOW,
    C_VALID_LOW,
    C_WR_ACK_LOW,
    C_WR_DATA_COUNT_WIDTH,
    C_WR_DEPTH,
    C_WR_PNTR_WIDTH,
    C_WR_RESPONSE_LATENCY
  )
  gen_fifo16
  (
    .WR_CLK(WR_CLK_2), 
    .RD_CLK(RD_CLK_2), 
    .RST(RST_2), 
    .DIN(DIN_2), 
    .WR_EN(WR_EN_2), 
    .RD_EN(RD_EN_2), 
    .PROG_EMPTY_THRESH(PROG_EMPTY_THRESH_2), 
    .PROG_EMPTY_THRESH_ASSERT(PROG_EMPTY_THRESH_ASSERT_2), 
    .PROG_EMPTY_THRESH_NEGATE(PROG_EMPTY_THRESH_NEGATE_2), 
    .PROG_FULL_THRESH(PROG_FULL_THRESH_2), 
    .PROG_FULL_THRESH_ASSERT(PROG_FULL_THRESH_ASSERT_2), 
    .PROG_FULL_THRESH_NEGATE(PROG_FULL_THRESH_NEGATE_2), 
    .DOUT(DOUT_I_2), 
    .FULL(FULL_I_2), 
    .ALMOST_FULL(ALMOST_FULL_I_2), 
    .WR_ACK(WR_ACK_I_2), 
    .OVERFLOW(OVERFLOW_I_2), 
    .EMPTY(EMPTY_I_2), 
    .ALMOST_EMPTY(ALMOST_EMPTY_I_2), 
    .VALID(VALID_I_2), 
    .UNDERFLOW(UNDERFLOW_I_2), 
    .PROG_FULL(PROG_FULL_I_2), 
    .PROG_EMPTY(PROG_EMPTY_I_2)
   );



/*******************************************************************************
 * Assign inputs based on implementation types, 'tie off' unused modules
 ******************************************************************************/
assign CLK_0           = (C_VERILOG_IMPL == 0) ? CLK           : 0;
assign WR_CLK_1        = (C_VERILOG_IMPL == 1) ? WR_CLK        : 0;
assign WR_CLK_2        = (C_VERILOG_IMPL == 2) ? WR_CLK        : 0;
assign RD_CLK_1        = (C_VERILOG_IMPL == 1) ? RD_CLK        : 0;
assign RD_CLK_2        = (C_VERILOG_IMPL == 2) ? RD_CLK        : 0;

assign RST_0           = (C_VERILOG_IMPL == 0) ? RST           : 0;
assign RST_1           = (C_VERILOG_IMPL == 1) ? RST           : 0;
assign RST_2           = (C_VERILOG_IMPL == 2) ? RST           : 0;

assign DIN_0           = (C_VERILOG_IMPL == 0) ? DIN           : 0;
assign DIN_1           = (C_VERILOG_IMPL == 1) ? DIN           : 0;
assign DIN_2           = (C_VERILOG_IMPL == 2) ? DIN           : 0;  
assign WR_EN_0         = (C_VERILOG_IMPL == 0) ? WR_EN         : 0;
assign WR_EN_1         = (C_VERILOG_IMPL == 1) ? WR_EN         : 0;
assign WR_EN_2         = (C_VERILOG_IMPL == 2) ? WR_EN         : 0;
assign RD_EN_0         = (C_VERILOG_IMPL == 0) ? RD_EN         : 0;
assign RD_EN_1         = (C_VERILOG_IMPL == 1) ? RD_EN         : 0;
assign RD_EN_2         = (C_VERILOG_IMPL == 2) ? RD_EN         : 0;

assign PROG_EMPTY_THRESH_0        = (C_VERILOG_IMPL == 0) ? PROG_EMPTY_THRESH        : 0;
assign PROG_EMPTY_THRESH_1        = (C_VERILOG_IMPL == 1) ? PROG_EMPTY_THRESH        : 0;
assign PROG_EMPTY_THRESH_2        = (C_VERILOG_IMPL == 2) ? PROG_EMPTY_THRESH        : 0;
assign PROG_EMPTY_THRESH_ASSERT_0 = (C_VERILOG_IMPL == 0) ? PROG_EMPTY_THRESH_ASSERT : 0;
assign PROG_EMPTY_THRESH_ASSERT_1 = (C_VERILOG_IMPL == 1) ? PROG_EMPTY_THRESH_ASSERT : 0;
assign PROG_EMPTY_THRESH_ASSERT_2 = (C_VERILOG_IMPL == 2) ? PROG_EMPTY_THRESH_ASSERT : 0;
assign PROG_EMPTY_THRESH_NEGATE_0 = (C_VERILOG_IMPL == 0) ? PROG_EMPTY_THRESH_NEGATE : 0;
assign PROG_EMPTY_THRESH_NEGATE_1 = (C_VERILOG_IMPL == 1) ? PROG_EMPTY_THRESH_NEGATE : 0;
assign PROG_EMPTY_THRESH_NEGATE_2 = (C_VERILOG_IMPL == 2) ? PROG_EMPTY_THRESH_NEGATE : 0;

assign PROG_FULL_THRESH_0         = (C_VERILOG_IMPL == 0) ? PROG_FULL_THRESH         : 0;
assign PROG_FULL_THRESH_1         = (C_VERILOG_IMPL == 1) ? PROG_FULL_THRESH         : 0;
assign PROG_FULL_THRESH_2         = (C_VERILOG_IMPL == 2) ? PROG_FULL_THRESH         : 0;
assign PROG_FULL_THRESH_ASSERT_0  = (C_VERILOG_IMPL == 0) ? PROG_FULL_THRESH_ASSERT  : 0;
assign PROG_FULL_THRESH_ASSERT_1  = (C_VERILOG_IMPL == 1) ? PROG_FULL_THRESH_ASSERT  : 0;
assign PROG_FULL_THRESH_ASSERT_2  = (C_VERILOG_IMPL == 2) ? PROG_FULL_THRESH_ASSERT  : 0;
assign PROG_FULL_THRESH_NEGATE_0  = (C_VERILOG_IMPL == 0) ? PROG_FULL_THRESH_NEGATE  : 0;
assign PROG_FULL_THRESH_NEGATE_1  = (C_VERILOG_IMPL == 1) ? PROG_FULL_THRESH_NEGATE  : 0;
assign PROG_FULL_THRESH_NEGATE_2  = (C_VERILOG_IMPL == 2) ? PROG_FULL_THRESH_NEGATE  : 0;
   

/*******************************************************************************
 * Assign outputs based on implementation types
 ******************************************************************************/
always @(
 DOUT_I_0 or DOUT_I_1 or DOUT_I_2 or 
 FULL_I_0 or FULL_I_1 or FULL_I_2 or 
 ALMOST_FULL_I_0 or ALMOST_FULL_I_1 or ALMOST_FULL_I_2 or 
 WR_ACK_I_0 or WR_ACK_I_1 or WR_ACK_I_2 or 
 OVERFLOW_I_0 or OVERFLOW_I_1 or OVERFLOW_I_2 or 
 EMPTY_I_0 or EMPTY_I_1 or EMPTY_I_2 or 
 ALMOST_EMPTY_I_0 or ALMOST_EMPTY_I_1 or ALMOST_EMPTY_I_2 or 
 VALID_I_0 or VALID_I_1 or VALID_I_2 or 
 UNDERFLOW_I_0 or UNDERFLOW_I_1 or UNDERFLOW_I_2 or 
 DATA_COUNT_I_0 or RD_DATA_COUNT_I_1 or WR_DATA_COUNT_I_1 or 
 PROG_FULL_I_0 or PROG_FULL_I_1 or PROG_FULL_I_2 or 
 PROG_EMPTY_I_0 or PROG_EMPTY_I_1 or PROG_EMPTY_I_2) 

  begin
    case(C_VERILOG_IMPL)
      0 : begin
	DOUT = DOUT_I_0;
        FULL = FULL_I_0;
        ALMOST_FULL = ALMOST_FULL_I_0;
        WR_ACK = WR_ACK_I_0;
        OVERFLOW = OVERFLOW_I_0;
        EMPTY = EMPTY_I_0;
        ALMOST_EMPTY = ALMOST_EMPTY_I_0;
        VALID = VALID_I_0;
        UNDERFLOW = UNDERFLOW_I_0; 
        DATA_COUNT = DATA_COUNT_I_0;
        RD_DATA_COUNT = 0;
        WR_DATA_COUNT = 0;
        PROG_FULL = PROG_FULL_I_0;
        PROG_EMPTY = PROG_EMPTY_I_0;
      end // case: 0
      1 : begin
	DOUT = DOUT_I_1;
        FULL = FULL_I_1;
        ALMOST_FULL = ALMOST_FULL_I_1;
        WR_ACK = WR_ACK_I_1;
        OVERFLOW = OVERFLOW_I_1;
        EMPTY = EMPTY_I_1;
        ALMOST_EMPTY = ALMOST_EMPTY_I_1;
        VALID = VALID_I_1;
        UNDERFLOW = UNDERFLOW_I_1; 
        DATA_COUNT = 0;
        RD_DATA_COUNT = RD_DATA_COUNT_I_1;
        WR_DATA_COUNT = WR_DATA_COUNT_I_1;
        PROG_FULL = PROG_FULL_I_1;
        PROG_EMPTY = PROG_EMPTY_I_1;
      end // case: 1
      2 : begin
	DOUT = DOUT_I_2;
        FULL = FULL_I_2;
        ALMOST_FULL = ALMOST_FULL_I_2;
        WR_ACK = WR_ACK_I_2;
        OVERFLOW = OVERFLOW_I_2;
        EMPTY = EMPTY_I_2;
        ALMOST_EMPTY = ALMOST_EMPTY_I_2;
        VALID = VALID_I_2;
        UNDERFLOW = UNDERFLOW_I_2; 
        DATA_COUNT = 0;
        RD_DATA_COUNT = 0;
        WR_DATA_COUNT = 0;
        PROG_FULL = PROG_FULL_I_2;
        PROG_EMPTY = PROG_EMPTY_I_2;
      end // case: 2
      default : begin
	DOUT = DOUT_I_1;
        FULL = FULL_I_1;
        ALMOST_FULL = ALMOST_FULL_I_1;
        WR_ACK = WR_ACK_I_1;
        OVERFLOW = OVERFLOW_I_1;
        EMPTY = EMPTY_I_1;
        ALMOST_EMPTY = ALMOST_EMPTY_I_1;
        VALID = VALID_I_1;
        UNDERFLOW = UNDERFLOW_I_1; 
        DATA_COUNT = 0;
        RD_DATA_COUNT = RD_DATA_COUNT_I_1;
        WR_DATA_COUNT = WR_DATA_COUNT_I_1;
        PROG_FULL = PROG_FULL_I_1;
        PROG_EMPTY = PROG_EMPTY_I_1;
      end // case: default
    endcase // case(C_VERILOG_IMPL)
  end // always

   
endmodule //fifo_generator_v2_0_bhv_ver
   





/*******************************************************************************
 * Declaration of asynchronous FIFO Module
 ******************************************************************************/
module fifo_generator_v2_0_bhv_ver_as
  (
    WR_CLK, RD_CLK, RST, DIN, WR_EN, RD_EN, 
    PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE, 
    PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE, 
    DOUT, FULL, ALMOST_FULL, WR_ACK, OVERFLOW, EMPTY, ALMOST_EMPTY, VALID,
    UNDERFLOW, RD_DATA_COUNT, WR_DATA_COUNT, PROG_FULL, PROG_EMPTY
   );

/******************************************************************************
 * Definition of Ports
 * 
 * 
 *****************************************************************************
 * Definition of Parameters 
 * 
 * 
 *****************************************************************************/

/******************************************************************************
 * Declare user parameters and their defaults
 *****************************************************************************/
 parameter  C_COMMON_CLOCK            = 0;
 parameter  C_COUNT_TYPE              = 0;
 parameter  C_DATA_COUNT_WIDTH        = 2;
 parameter  C_DEFAULT_VALUE           = "";
 parameter  C_DIN_WIDTH               = 8;
 parameter  C_DOUT_RST_VAL            = "";
 parameter  C_DOUT_WIDTH              = 8;
 parameter  C_ENABLE_RLOCS            = 0;
 parameter  C_FAMILY                  = "virtex2"; //Not allowed in Verilog model
 parameter  C_HAS_ALMOST_EMPTY        = 0;
 parameter  C_HAS_ALMOST_FULL         = 0;
 parameter  C_HAS_BACKUP              = 0;
 parameter  C_HAS_DATA_COUNT          = 0;
 parameter  C_HAS_MEMINIT_FILE        = 0;
 parameter  C_HAS_OVERFLOW            = 0;
 parameter  C_HAS_RD_DATA_COUNT       = 0;
 parameter  C_HAS_RD_RST              = 0;
 parameter  C_HAS_RST                 = 0;
 parameter  C_HAS_UNDERFLOW           = 0;
 parameter  C_HAS_VALID               = 0;
 parameter  C_HAS_WR_ACK              = 0;
 parameter  C_HAS_WR_DATA_COUNT       = 0;
 parameter  C_HAS_WR_RST              = 0;
 parameter  C_IMPLEMENTATION_TYPE     = 0;   
 parameter  C_INIT_WR_PNTR_VAL        = 0;
 parameter  C_MEMORY_TYPE             = 1;
 parameter  C_MIF_FILE_NAME           = "";
 parameter  C_OPTIMIZATION_MODE       = 0;
 parameter  C_OVERFLOW_LOW            = 0;
 parameter  C_PRELOAD_LATENCY         = 1;
 parameter  C_PRELOAD_REGS            = 0;
 parameter  C_PROG_EMPTY_THRESH_ASSERT_VAL       = 0;
 parameter  C_PROG_EMPTY_THRESH_NEGATE_VAL       = 0;
 parameter  C_PROG_EMPTY_TYPE       = 0;
 parameter  C_PROG_FULL_THRESH_ASSERT_VAL        = 0;
 parameter  C_PROG_FULL_THRESH_NEGATE_VAL        = 0;
 parameter  C_PROG_FULL_TYPE        = 0;
 parameter  C_RD_DATA_COUNT_WIDTH     = 2;
 parameter  C_RD_DEPTH                = 256;
 parameter  C_RD_PNTR_WIDTH           = 8;
 parameter  C_UNDERFLOW_LOW           = 0;
 parameter  C_VALID_LOW               = 0;
 parameter  C_WR_ACK_LOW              = 0;
 parameter  C_WR_DATA_COUNT_WIDTH     = 2;
 parameter  C_WR_DEPTH                = 256;
 parameter  C_WR_PNTR_WIDTH           = 8;
 parameter  C_WR_RESPONSE_LATENCY     = 1;
 
/******************************************************************************
 * Declare Input and Output Ports
 *****************************************************************************/
 input [C_DIN_WIDTH-1:0]          DIN;
 input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH;
 input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_ASSERT;
 input [C_RD_PNTR_WIDTH-1:0]      PROG_EMPTY_THRESH_NEGATE;
 input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH;
 input [C_WR_PNTR_WIDTH-1:0]      PROG_FULL_THRESH_ASSERT;