_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity syndcell_7 is
    port(
        recword         : in     vl_logic_vector(7 downto 0);
        clock           : in     vl_logic;
        enable          : in     vl_logic;
        hold            : in     vl_logic;
        synvalue7       : out    vl_logic_vector(7 downto 0)
    );
end syndcell_7;