_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 37 行

library verilog;
use verilog.vl_types.all;
entity CSEEblock is
    generic(
        st0             : integer := 0;
        st1             : integer := 1
    );
    port(
        lambda0         : in     vl_logic_vector(7 downto 0);
        lambda1         : in     vl_logic_vector(7 downto 0);
        lambda2         : in     vl_logic_vector(7 downto 0);
        lambda3         : in     vl_logic_vector(7 downto 0);
        lambda4         : in     vl_logic_vector(7 downto 0);
        lambda5         : in     vl_logic_vector(7 downto 0);
        lambda6         : in     vl_logic_vector(7 downto 0);
        lambda7         : in     vl_logic_vector(7 downto 0);
        lambda8         : in     vl_logic_vector(7 downto 0);
        homega0         : in     vl_logic_vector(7 downto 0);
        homega1         : in     vl_logic_vector(7 downto 0);
        homega2         : in     vl_logic_vector(7 downto 0);
        homega3         : in     vl_logic_vector(7 downto 0);
        homega4         : in     vl_logic_vector(7 downto 0);
        homega5         : in     vl_logic_vector(7 downto 0);
        homega6         : in     vl_logic_vector(7 downto 0);
        homega7         : in     vl_logic_vector(7 downto 0);
        errorvalue      : out    vl_logic_vector(7 downto 0);
        clock1          : in     vl_logic;
        clock2          : in     vl_logic;
        active_csee     : in     vl_logic;
        reset           : in     vl_logic;
        lastdataout     : in     vl_logic;
        evalerror       : in     vl_logic;
        en_outfifo      : in     vl_logic;
        rootcntr        : out    vl_logic_vector(3 downto 0)
    );
end CSEEblock;