_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 27 行

library verilog;
use verilog.vl_types.all;
entity control is
    generic(
        st0             : integer := 0;
        st1             : integer := 1;
        st2             : integer := 2;
        st3             : integer := 3;
        st4             : integer := 4;
        st5             : integer := 5
    );
    port(
        delta0_in       : in     vl_logic_vector(7 downto 0);
        gamma           : out    vl_logic_vector(7 downto 0);
        active_kes      : in     vl_logic;
        reset           : in     vl_logic;
        delta0_out      : out    vl_logic_vector(7 downto 0);
        iter_control    : out    vl_logic;
        finish          : out    vl_logic;
        load            : out    vl_logic;
        init            : out    vl_logic;
        hold            : out    vl_logic;
        clock1          : in     vl_logic;
        clock2          : in     vl_logic
    );
end control;