_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 37 行

library verilog;
use verilog.vl_types.all;
entity SCblock is
    generic(
        st0             : integer := 0;
        st1             : integer := 1;
        st2             : integer := 2
    );
    port(
        recword         : in     vl_logic_vector(7 downto 0);
        clock1          : in     vl_logic;
        clock2          : in     vl_logic;
        active_sc       : in     vl_logic;
        reset           : in     vl_logic;
        syndvalue0      : out    vl_logic_vector(7 downto 0);
        syndvalue1      : out    vl_logic_vector(7 downto 0);
        syndvalue2      : out    vl_logic_vector(7 downto 0);
        syndvalue3      : out    vl_logic_vector(7 downto 0);
        syndvalue4      : out    vl_logic_vector(7 downto 0);
        syndvalue5      : out    vl_logic_vector(7 downto 0);
        syndvalue6      : out    vl_logic_vector(7 downto 0);
        syndvalue7      : out    vl_logic_vector(7 downto 0);
        syndvalue8      : out    vl_logic_vector(7 downto 0);
        syndvalue9      : out    vl_logic_vector(7 downto 0);
        syndvalue10     : out    vl_logic_vector(7 downto 0);
        syndvalue11     : out    vl_logic_vector(7 downto 0);
        syndvalue12     : out    vl_logic_vector(7 downto 0);
        syndvalue13     : out    vl_logic_vector(7 downto 0);
        syndvalue14     : out    vl_logic_vector(7 downto 0);
        syndvalue15     : out    vl_logic_vector(7 downto 0);
        errdetect       : out    vl_logic;
        en_sccell       : in     vl_logic;
        evalsynd        : in     vl_logic;
        holdsynd        : in     vl_logic
    );
end SCblock;