_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 14 行

library verilog;
use verilog.vl_types.all;
entity PE_24 is
    port(
        delta           : in     vl_logic_vector(7 downto 0);
        clock           : in     vl_logic;
        load            : in     vl_logic;
        init            : in     vl_logic;
        hold            : in     vl_logic;
        iter_control    : in     vl_logic;
        delta_cflex_out : out    vl_logic_vector(7 downto 0)
    );
end PE_24;