cseeblock.v

Reed-Solomon 信道编码广泛应用于DVB中

//***************************************************************//
// Chien Search and Error Evaluator (CSEE) block find            //
// error location (Xi) while determine its error magnitude (Yi). //
// This CSEE block implement Chien search algorithm to find      //
// location of an error and Fourney Formula to compute the error //
// error value. Error value will be outputted serially and has   //
// to be synchronous with output of FIFO Register.               //
//***************************************************************//

module CSEEblock(lambda0, lambda1, lambda2, lambda3, lambda4,
                  lambda5, lambda6, lambda7, lambda8, homega0, homega1, homega2,
                  homega3, homega4, homega5, homega6, homega7, errorvalue, clock1,
                  clock2, active_csee, reset, lastdataout, evalerror,
                  en_outfifo, rootcntr);

input [7:0] lambda0, lambda1, lambda2, lambda3, lambda4,
            lambda5, lambda6, lambda7, lambda8;
input [7:0] homega0, homega1, homega2, homega3, homega4, 
            homega5, homega6, homega7;
input clock1, clock2, active_csee, reset;
input lastdataout, evalerror, en_outfifo;
output [7:0] errorvalue;
output [3:0] rootcntr;

wire [7:0] cs0_out, cs1_out, cs2_out, cs3_out, cs4_out, cs5_out,
           cs6_out, cs7_out, cs8_out;
wire [7:0] fn0_out, fn1_out, fn2_out, fn3_out, fn4_out, fn5_out, 
           fn6_out, fn7_out, patch;
wire [7:0] lambda11, lambda22, lambda33, lambda44, lambda66, 
           lambda77, lambda88;
wire [7:0] homega11, homega22, homega33, homega44, homega66,
           homega77;
wire [7:0] oddlambda, evenlambda, lambdaval;
wire [7:0] omegaval, numerator, fourney_out, inv_oddlambda;
wire zerodetect;
wire [7:0] andtree_out;
reg load;
reg enrootcnt;
reg [3:0] rootcntr;

parameter st0=0, st1=1;
reg state, nxt_state;

//*****//
// FSM //
//*****//
always@(posedge clock2 or negedge reset)
begin
    if(~reset)
       state = st0;
    else
       state = nxt_state;
end
 
always@(state or active_csee or lastdataout)
begin
    case(state)
    st0   : begin
            if(active_csee)
               nxt_state = st1;
            else
               nxt_state = st0;
            end
    st1   : begin
             if(lastdataout)
                nxt_state = st0;
             else
                nxt_state = st1;
            end
    default: nxt_state = st0;
    endcase
end

always@(state)
begin
    case(state)
    st0   : begin
            load = 0;
            enrootcnt = 0;
            end
    st1   : begin
            load = 1;
            enrootcnt = 1;
            end
    default: begin
             load = 0;
             enrootcnt = 0;
             end
    endcase
end

//********************************//
// Counter for roots of lambda(x) //
// with synchronous hold          // 
//********************************//
always@(posedge clock2)
begin
    if(enrootcnt)
       begin
       if(zerodetect)
          rootcntr <= rootcntr + 1;
       else
          rootcntr <= rootcntr;
       end
    else
       rootcntr <= 4'b0;
end

               
//*******************//
// Chien Seach block //
//*******************//
degree51_cell cspre1(lambda1, lambda11);
degree102_cell cspre2(lambda2, lambda22);
degree153_cell cspre3(lambda3, lambda33);
degree204_cell cspre4(lambda4, lambda44);
degree51_cell cspre6(lambda6, lambda66);
degree102_cell cspre7(lambda7, lambda77);
degree153_cell cspre8(lambda8, lambda88);

degree0_cell cs0_cell(lambda0, cs0_out, clock1, load, evalerror);                  
degree1_cell cs1_cell(lambda11, cs1_out, clock1, load, evalerror);
degree2_cell cs2_cell(lambda22, cs2_out, clock1, load, evalerror);
degree3_cell cs3_cell(lambda33, cs3_out, clock1, load, evalerror);
degree4_cell cs4_cell(lambda44, cs4_out, clock1, load, evalerror);
degree5_cell cs5_cell(lambda5, cs5_out, clock1, load, evalerror);
degree6_cell cs6_cell(lambda66, cs6_out, clock1, load, evalerror);
degree7_cell cs7_cell(lambda77, cs7_out, clock1, load, evalerror);
degree8_cell cs8_cell(lambda88, cs8_out, clock1, load, evalerror);

assign oddlambda = (cs1_out ^ cs3_out) ^ (cs5_out ^ cs7_out);
assign evenlambda = ((cs0_out ^ cs2_out) ^ cs4_out) ^ (cs6_out ^ cs8_out);
assign lambdaval = oddlambda ^ evenlambda;

//*****************************************//
// Error Evaluator (Fourney Formula) block //
//*****************************************//
degree51_cell fnpre1(homega1, homega11);
degree102_cell fnpre2(homega2, homega22);
degree153_cell fnpre3(homega3, homega33);
degree204_cell fnpre4(homega4, homega44);
degree51_cell fnpre6(homega6, homega66);
degree102_cell fnpre7(homega7, homega77);


degree0_cell fn0_cell(homega0, fn0_out, clock1, load, evalerror);                  
degree1_cell fn1_cell(homega11, fn1_out, clock1, load, evalerror);
degree2_cell fn2_cell(homega22, fn2_out, clock1, load, evalerror);
degree3_cell fn3_cell(homega33, fn3_out, clock1, load, evalerror);
degree4_cell fn4_cell(homega44, fn4_out, clock1, load, evalerror);
degree5_cell fn5_cell(homega5, fn5_out, clock1, load, evalerror);
degree6_cell fn6_cell(homega66, fn6_out, clock1, load, evalerror);
degree7_cell fn7_cell(homega77, fn7_out, clock1, load, evalerror);

degree16_cell patch_cell(8'b00001010, patch, clock1, load, evalerror);

assign omegaval = ((fn0_out ^ fn1_out) ^ (fn2_out ^ fn3_out)) ^ 
                  ((fn4_out ^ fn5_out) ^ (fn6_out ^ fn7_out));

inverscomb invers(oddlambda, inv_oddlambda);
lcpmult multiplier1(omegaval, patch, numerator);
lcpmult multiplier(inv_oddlambda, numerator, fourney_out);

//*****************************//
// Zero detect and error value //
//*****************************//
assign zerodetect = ~(((lambdaval[0] | lambdaval[1]) | 
                     (lambdaval[2]| lambdaval[3])) | 
                     ((lambdaval[4] | lambdaval[5]) |
                     (lambdaval[6] | lambdaval[7])));
assign andtree_out[0] = fourney_out[0] & zerodetect;
assign andtree_out[1] = fourney_out[1] & zerodetect;
assign andtree_out[2] = fourney_out[2] & zerodetect;
assign andtree_out[3] = fourney_out[3] & zerodetect;
assign andtree_out[4] = fourney_out[4] & zerodetect;
assign andtree_out[5] = fourney_out[5] & zerodetect;
assign andtree_out[6] = fourney_out[6] & zerodetect;
assign andtree_out[7] = fourney_out[7] & zerodetect;

//assign errorvalue = andtree_out;
register8_wl erroreg(andtree_out, errorvalue, clock2, en_outfifo);

endmodule


//******************************************************//
// Modul-modul chien search cell dibentuk dgn perkalian //
//***********************************************//
// Module for terms whose degree is zero         //
//***********************************************//
module degree0_cell(in, out, clock, load, compute);

input [7:0] in;
output [7:0] out;
input clock, compute, load;
wire [7:0] outmux, outreg;

register8_wl register(outmux, outreg, clock, load);
mux2_to_1 multiplex(in, outreg, outmux, compute);
assign out = outreg;

endmodule


//********************************************************//
// Module that computes term with degree one.             //
// Constructed by a variable-constant multiplier with     //
// alpha^1 as constant.                                   //
//********************************************************//
module degree1_cell(in, out, clock, load, compute);

input [7:0] in;
output [7:0] out;
input clock, load, compute;
wire [7:0] outmux;
wire [7:0] outmult, outreg;

register8_wl register(outmux, outreg, clock, load);
mux2_to_1 multiplexer(in, outmult, outmux, compute);

//Multipy variable-alpha^1
assign outmult[0] = outreg[7];
assign outmult[1] = outreg[0];
assign outmult[2] = outreg[1] ^ outreg[7];
assign outmult[3] = outreg[2] ^ outreg[7];
assign outmult[4] = outreg[3] ^ outreg[7];
assign outmult[5] = outreg[4];
assign outmult[6] = outreg[5];
assign outmult[7] = outreg[6];

assign out = outreg;

endmodule


//********************************************************//
// Module that computes term with degree two.
// Constructed by a variable-constant multiplier with 
// alpha^2 as constant.                                   //
//********************************************************//
module degree2_cell(in, out, clock, load, compute);

input [7:0] in;
output [7:0] out;
input clock, load, compute;
wire [7:0] outmux;
wire [7:0] outmult, outreg;

register8_wl register(outmux, outreg, clock, load);
mux2_to_1 multiplexer(in, outmult, outmux, compute);

//Multipy variable-alpha^2
assign outmult[0] = outreg[6];
assign outmult[1] = outreg[7];
assign outmult[2] = outreg[0] ^ outreg[6];
assign outmult[3] = (outreg[1] ^ outreg[6]) ^ outreg[7];
assign outmult[4] = (outreg[2] ^ outreg[6]) ^ outreg[7];
assign outmult[5] = outreg[3] ^ outreg[7];
assign outmult[6] = outreg[4];
assign outmult[7] = outreg[5];

assign out = outreg;

endmodule

//********************************************************//
// Module that computes term with degree three.           //
// Constructed by a variable-constant multiplier with     //
// alpha^3 as constant.                                   //
//********************************************************//
module degree3_cell(in, out, clock, load, compute);

input [7:0] in;
output [7:0] out;
input clock, load, compute;
wire [7:0] outmux;
wire [7:0] outmult, outreg;

register8_wl register(outmux, outreg, clock, load);
mux2_to_1 multiplexer(in, outmult, outmux, compute);

//Multipy variable-alpha^3
assign outmult[0] = outreg[5];
assign outmult[1] = outreg[6];
assign outmult[2] = outreg[5] ^ outreg[7];
assign outmult[3] = (outreg[0] ^ outreg[5]) ^ outreg[6];
assign outmult[4] = (outreg[1] ^ outreg[5]) ^ (outreg[6] ^ outreg[7]);
assign outmult[5] = (outreg[2] ^ outreg[6]) ^ outreg[7];
assign outmult[6] = outreg[3] ^ outreg[7];
assign outmult[7] = outreg[4];

assign out = outreg;

endmodule


//********************************************************//
// Module that computes term with degree four.           //
// Constructed by a variable-constant multiplier with     //
// alpha^4 as constant.                                   //
//********************************************************//
module degree4_cell(in, out, clock, load, compute);

input [7:0] in;
output [7:0] out;
input clock, load, compute;
wire [7:0] outmux;
wire [7:0] outmult, outreg;

register8_wl register(outmux, outreg, clock, load);
mux2_to_1 multiplexer(in, outmult, outmux, compute);

//Multipy variable-alpha^4
assign outmult[0] = outreg[4];
assign outmult[1] = outreg[5];
assign outmult[2] = outreg[4] ^ outreg[6];
assign outmult[3] = (outreg[4] ^ outreg[5]) ^ outreg[7];
assign outmult[4] = (outreg[0] ^ outreg[4]) ^ (outreg[5] ^ outreg[6]);
assign outmult[5] = (outreg[1] ^ outreg[5]) ^ (outreg[6] ^ outreg[7]);
assign outmult[6] = (outreg[2] ^ outreg[6]) ^ outreg[7];
assign outmult[7] = outreg[3] ^ outreg[7];

assign out = outreg;

endmodule

//********************************************************//