common_modules.v

Reed-Solomon 信道编码广泛应用于DVB中

//**********************************************//
//Register 8 bit with synchronous load and hold //
//**********************************************//
module register8_wlh(datain, dataout, load, hold, clock);
parameter width=8;

input [width-1:0] datain;
input load, hold;
input clock;
output [width-1:0] dataout;
reg [width-1:0] out;

always @(posedge clock)
begin
    if(load)
       out <= datain;
    else if(hold)
       out <= out;
    else
       out <= 8'b0;
end

assign dataout = out;

endmodule

//**************************************//
// Register 8 bit with synchronous load //
//**************************************//
module register8_wl(datain, dataout, clock, load);
parameter width=8;

input [width-1:0] datain;
output [width-1:0] dataout;
input clock, load;
reg [width-1:0] dataout;

always@(posedge clock)
begin
    if(load)
       dataout <= datain;
    else
       dataout <= 8'b0;
end

endmodule


//**************//
//GF(2^8) Adder //
//**************//
module gfadder(in1, in2, out);
    
input [0:7] in1, in2;
output [0:7] out;

assign out[7] = in1[7] ^ in2[7];
assign out[6] = in1[6] ^ in2[6];
assign out[5] = in1[5] ^ in2[5];    
assign out[4] = in1[4] ^ in2[4];
assign out[3] = in1[3] ^ in2[3];
assign out[2] = in1[2] ^ in2[2];
assign out[1] = in1[1] ^ in2[1];
assign out[0] = in1[0] ^ in2[0];

endmodule

//*************************//
// Multiplexer 2 to 1 8bit //
//*************************//
module mux2_to_1(in1, in2 , out, sel);

input [7:0] in1, in2;
input sel;
output [7:0] out;
reg [7:0] out;

always@(sel or in1 or in2)
begin
    case(sel)
        0   : out = in1;
        1   : out = in2;
        default: out = in1;
    endcase
end
endmodule

//*********************************************//
// GF(2^8) parallel multiplier is based on     //
// the design proposed by M. Anwar Hasan &     //
// A. Reyhani-Masoleh in their paper entitled  //
// "Low Complexity Bit Parallel Architectures  //
// for Polynomial Basis Multiplication over    //
// GF(2^m)" published in IEEE Transactions On  //
// Computer August 2004.                       //
//*********************************************//
module lcpmult(in1, in2, out);
   
     input [7:0] in1, in2; //in1[4] & in2[4] is MSB
   output [7:0] out;
   
   wire [7:0] intvald; //intermediate val d
   wire [0:6] intvale; //intermediate val e
   assign intvald[0]=in1[0]&in2[0];
   assign intvald[1]=(in1[0]&in2[1])^(in1[1]&in2[0]);
   assign intvald[2]=(in1[0]&in2[2])^((in1[1]&in2[1])^(in1[2]&in2[0]));
   assign intvald[3]=((in1[0]&in2[3])^(in1[1]&in2[2]))^((in1[2]&in2[1])^(in1[3]&in2[0]));
   assign intvald[4]=(in1[0]&in2[4])^(((in1[1]&in2[3])^(in1[2]&in2[2]))^((in1[3]&in2[1])^(in1[4]&in2[0])));
   assign intvald[5]=((in1[0]&in2[5])^(in1[1]&in2[4]))^(((in1[2]&in2[3])^(in1[3]&in2[2]))^((in1[4]&in2[1])^(in1[5]&in2[0])));
   assign intvald[6]=((in1[0]&in2[6])^((in1[1]&in2[5])^(in1[2]&in2[4])))^(((in1[3]&in2[3])^(in1[4]&in2[2]))^((in1[5]&in2[1])^(in1[6]&in2[0])));
   assign intvald[7]=(((in1[0]&in2[7])^(in1[1]&in2[6]))^((in1[2]&in2[5])^(in1[3]&in2[4])))^(((in1[4]&in2[3])^(in1[5]&in2[2]))^((in1[6]&in2[1])^(in1[7]&in2[0])));
   assign intvale[0]=(((in1[1]&in2[7])^(in1[2]&in2[6]))^((in1[3]&in2[5])^(in1[4]&in2[4])))^(((in1[5]&in2[3])^(in1[6]&in2[2]))^(in1[7]&in2[1]));
   assign intvale[1]=(((in1[2]&in2[7])^(in1[3]&in2[6]))^((in1[4]&in2[5])^(in1[5]&in2[4])))^((in1[6]&in2[3])^(in1[7]&in2[2]));
   assign intvale[2]=(((in1[3]&in2[7])^(in1[4]&in2[6]))^((in1[5]&in2[5])^(in1[6]&in2[4])))^(in1[7]&in2[3]);
   assign intvale[3]=((in1[4]&in2[7])^(in1[5]&in2[6]))^((in1[6]&in2[5])^(in1[7]&in2[4]));
   assign intvale[4]=((in1[5]&in2[7])^(in1[6]&in2[6]))^(in1[7]&in2[5]);
   assign intvale[5]=(in1[6]&in2[7])^(in1[7]&in2[6]);
   assign intvale[6]=in1[7]&in2[7];

   assign out[0] = ((intvald[0] ^ intvale[0])^(intvale[4]^intvale[5]))^intvale[6];
   assign out[1] = (intvald[1] ^ intvale[1])^(intvale[5]^intvale[6]);
   assign out[2] = ((intvald[2] ^ intvale[0]) ^(intvale[2]^intvale[4]))^intvale[5];
   assign out[3] = ((intvald[3] ^ intvale[0]) ^(intvale[1]^intvale[3]))^intvale[4];
   assign out[4] = ((intvald[4] ^ intvale[0]) ^(intvale[1]^intvale[2]))^intvale[6];
   assign out[5] = (intvald[5]^intvale[3])^(intvale[2]^intvale[1]);
   assign out[6] = (intvald[6]^intvale[4])^(intvale[3]^intvale[2]);
   assign out[7] = (intvald[7]^intvale[3])^(intvale[4]^intvale[5]);
endmodule