asyncfifo256.edn

Reed-Solomon 信道编码广泛应用于DVB中

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2007 8 5 15 53 50)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 7.1.04i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2004 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_wr_response_latency = 1 ")
       (comment "c_has_rd_data_count = 0 ")
       (comment "c_din_width = 8 ")
       (comment "c_has_wr_data_count = 0 ")
       (comment "InstanceName = asyncfifo256 ")
       (comment "c_implementation_type = 2 ")
       (comment "c_family = virtex4 ")
       (comment "c_has_wr_rst = 0 ")
       (comment "c_underflow_low = 0 ")
       (comment "c_has_meminit_file = 0 ")
       (comment "c_has_overflow = 0 ")
       (comment "c_preload_latency = 1 ")
       (comment "c_dout_width = 8 ")
       (comment "c_rd_depth = 256 ")
       (comment "c_default_value = BlankString ")
       (comment "c_mif_file_name = BlankString ")
       (comment "c_has_underflow = 0 ")
       (comment "c_has_almost_full = 0 ")
       (comment "c_has_rd_rst = 0 ")
       (comment "c_has_rst = 1 ")
       (comment "c_data_count_width = 2 ")
       (comment "c_has_wr_ack = 0 ")
       (comment "c_wr_ack_low = 0 ")
       (comment "c_common_clock = 0 ")
       (comment "c_rd_pntr_width = 8 ")
       (comment "c_has_almost_empty = 0 ")
       (comment "c_rd_data_count_width = 2 ")
       (comment "c_enable_rlocs = 0 ")
       (comment "c_wr_pntr_width = 8 ")
       (comment "c_overflow_low = 0 ")
       (comment "c_optimization_mode = 0 ")
       (comment "c_prog_empty_type = 0 ")
       (comment "c_wr_data_count_width = 2 ")
       (comment "c_preload_regs = 0 ")
       (comment "c_dout_rst_val = 1 ")
       (comment "c_has_data_count = 0 ")
       (comment "c_prog_full_thresh_negate_val = 768 ")
       (comment "c_wr_depth = 256 ")
       (comment "c_prog_empty_thresh_negate_val = 256 ")
       (comment "c_init_wr_pntr_val = 0 ")
       (comment "c_prog_empty_thresh_assert_val = 256 ")
       (comment "c_has_valid = 0 ")
       (comment "c_prog_full_thresh_assert_val = 768 ")
       (comment "c_has_backup = 0 ")
       (comment "c_valid_low = 0 ")
       (comment "c_prim_fifo_type = 1024 ")
       (comment "c_count_type = 0 ")
       (comment "c_prog_full_type = 0 ")
       (comment "c_memory_type = 1 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
   )
   (external asyncfifo256_fifo_generator_v2_0_as_1_lib (edifLevel 0)
       (technology (numberDefinition))
       (cell asyncfifo256_fifo_generator_v2_0_as_1 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port wr_clk (direction INPUT))
                   (port rd_clk (direction INPUT))
                   (port rst (direction INPUT))
                   (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT))
                   (port wr_en (direction INPUT))
                   (port rd_en (direction INPUT))
                   (port ( array ( rename prog_full_thresh "prog_full_thresh<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh_assert "prog_full_thresh_assert<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename prog_full_thresh_negate "prog_full_thresh_negate<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh "prog_empty_thresh<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh_assert "prog_empty_thresh_assert<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename prog_empty_thresh_negate "prog_empty_thresh_negate<7:0>") 8 ) (direction INPUT))
                   (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT))
                   (port full (direction OUTPUT))
                   (port almost_full (direction OUTPUT))
                   (port wr_ack (direction OUTPUT))
                   (port overflow (direction OUTPUT))
                   (port empty (direction OUTPUT))
                   (port almost_empty (direction OUTPUT))
                   (port valid (direction OUTPUT))
                   (port underflow (direction OUTPUT))
                   (port ( array ( rename rd_data_count "rd_data_count<1:0>") 2 ) (direction OUTPUT))
                   (port ( array ( rename wr_data_count "wr_data_count<1:0>") 2 ) (direction OUTPUT))
                   (port prog_full (direction OUTPUT))
                   (port prog_empty (direction OUTPUT))
                   (port ( array ( rename debug_wr_pntr "debug_wr_pntr<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_rd_pntr "debug_rd_pntr<7:0>") 8 ) (direction OUTPUT))
                   (port debug_ram_wr_en (direction OUTPUT))
                   (port debug_ram_rd_en (direction OUTPUT))
                   (port ( array ( rename debug_wr_pntr_w "debug_wr_pntr_w<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_wr_pntr_plus1_w "debug_wr_pntr_plus1_w<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_wr_pntr_plus2_w "debug_wr_pntr_plus2_w<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_wr_pntr_r "debug_wr_pntr_r<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_rd_pntr_r "debug_rd_pntr_r<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_rd_pntr_plus1_r "debug_rd_pntr_plus1_r<7:0>") 8 ) (direction OUTPUT))
                   (port ( array ( rename debug_rd_pntr_w "debug_rd_pntr_w<7:0>") 8 ) (direction OUTPUT))
                   (port debug_ram_empty (direction OUTPUT))
                   (port debug_ram_full (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell asyncfifo256
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( array ( rename din "din<7:0>") 8 ) (direction INPUT))
   (port ( rename rd_clk "rd_clk") (direction INPUT))
   (port ( rename rd_en "rd_en") (direction INPUT))
   (port ( rename rst "rst") (direction INPUT))
   (port ( rename wr_clk "wr_clk") (direction INPUT))
   (port ( rename wr_en "wr_en") (direction INPUT))
   (port ( array ( rename dout "dout<7:0>") 8 ) (direction OUTPUT))
   (port ( rename empty "empty") (direction OUTPUT))
   (port ( rename full "full") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU2
      (viewRef view_1 (cellRef asyncfifo256_fifo_generator_v2_0_as_1 (libraryRef asyncfifo256_fifo_generator_v2_0_as_1_lib)))
   )
   (net (rename N81 "din<7>")
    (joined
      (portRef (member din 0))
      (portRef (member din 0) (instanceRef BU2))
    )
   )
   (net (rename N82 "din<6>")
    (joined
      (portRef (member din 1))
      (portRef (member din 1) (instanceRef BU2))
    )
   )
   (net (rename N83 "din<5>")
    (joined
      (portRef (member din 2))
      (portRef (member din 2) (instanceRef BU2))
    )
   )
   (net (rename N84 "din<4>")
    (joined
      (portRef (member din 3))
      (portRef (member din 3) (instanceRef BU2))
    )
   )
   (net (rename N85 "din<3>")
    (joined
      (portRef (member din 4))
      (portRef (member din 4) (instanceRef BU2))
    )
   )
   (net (rename N86 "din<2>")
    (joined
      (portRef (member din 5))
      (portRef (member din 5) (instanceRef BU2))
    )
   )
   (net (rename N87 "din<1>")
    (joined
      (portRef (member din 6))
      (portRef (member din 6) (instanceRef BU2))
    )
   )
   (net (rename N88 "din<0>")
    (joined
      (portRef (member din 7))
      (portRef (member din 7) (instanceRef BU2))
    )
   )
   (net (rename N137 "rd_clk")
    (joined
      (portRef rd_clk)
      (portRef rd_clk (instanceRef BU2))
    )
   )
   (net (rename N138 "rd_en")
    (joined
      (portRef rd_en)
      (portRef rd_en (instanceRef BU2))
    )
   )
   (net (rename N140 "rst")
    (joined
      (portRef rst)
      (portRef rst (instanceRef BU2))
    )
   )
   (net (rename N141 "wr_clk")
    (joined
      (portRef wr_clk)
      (portRef wr_clk (instanceRef BU2))
    )
   )
   (net (rename N142 "wr_en")
    (joined
      (portRef wr_en)
      (portRef wr_en (instanceRef BU2))
    )
   )
   (net (rename N148 "dout<7>")
    (joined
      (portRef (member dout 0))
      (portRef (member dout 0) (instanceRef BU2))
    )
   )
   (net (rename N149 "dout<6>")
    (joined
      (portRef (member dout 1))
      (portRef (member dout 1) (instanceRef BU2))
    )
   )
   (net (rename N150 "dout<5>")
    (joined
      (portRef (member dout 2))
      (portRef (member dout 2) (instanceRef BU2))
    )
   )
   (net (rename N151 "dout<4>")
    (joined
      (portRef (member dout 3))
      (portRef (member dout 3) (instanceRef BU2))
    )
   )
   (net (rename N152 "dout<3>")
    (joined
      (portRef (member dout 4))
      (portRef (member dout 4) (instanceRef BU2))
    )
   )
   (net (rename N153 "dout<2>")
    (joined
      (portRef (member dout 5))
      (portRef (member dout 5) (instanceRef BU2))
    )
   )
   (net (rename N154 "dout<1>")
    (joined
      (portRef (member dout 6))
      (portRef (member dout 6) (instanceRef BU2))
    )
   )
   (net (rename N155 "dout<0>")
    (joined
      (portRef (member dout 7))
      (portRef (member dout 7) (instanceRef BU2))
    )
   )
   (net (rename N156 "empty")
    (joined
      (portRef empty)
      (portRef empty (instanceRef BU2))
    )
   )
   (net (rename N157 "full")
    (joined
      (portRef full)
      (portRef full (instanceRef BU2))
    )
   )
))))
(design asyncfifo256 (cellRef asyncfifo256 (libraryRef test_lib))
  (property X_CORE_INFO (string "fifo_generator_v2_0, Coregen 7.1.04i"))
  (property PART (string "xc4vlx100-ff1513-12") (owner "Xilinx")))
)