fifo_register.v

Reed-Solomon 信道编码广泛应用于DVB中

//********************************************************//
// FIFO Register stores 204 recieved word symbols          //
// instance core generator fifo256 module                 //
//********************************************************//
module fifo_register(clock1, clock2,   
                     en_outfifo, en_infifo, datain, dataout,nrst);
input clock1, clock2,nrst;
//input shift_fifo, hold_fifo, en_outfifo, en_infifo;
input en_outfifo, en_infifo;
input [7:0] datain;
output [7:0] dataout;

wire rd_clk,wr_clk;
wire empty,full;
wire[7:0] din,dout;
wire rd_en,rst,wr_en;

assign rd_clk=clock2;
assign wr_clk=clock1;
//assign din=en_infifo?datain:8'h0;
assign din=datain;
//assign rd_en=en_outfifo&shift_fifo;
assign rd_en=en_outfifo;
//assign rst=~(nrst|hold_fifo);
assign rst=~nrst;
//assign wr_en=en_infifo&shift_fifo;
assign wr_en=en_infifo;

// Output register operates on clock2 to synchronize with //
// output of CSEE.                                        //

//register5_wl outreg(dout, dataout, clock2, en_outfifo);
assign dataout =dout;
//fifo256 instanse,which generated by Xilinx core generator
asyncfifo256 asyncfifo256(
	din,
	rd_clk,
	rd_en,
	rst,
	wr_clk,
	wr_en,
	dout,
	empty,
	full);

endmodule