scblock.v

Reed-Solomon 信道编码广泛应用于DVB中

assign outmult[1] = (outreg[3] ^ outreg[7]);
assign outmult[0] = (outreg[2] ^ outreg[6] ^ outreg[7]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue6 = outreg;

endmodule

//***************************************************//
//syndcell_7 computes R(alpha^7) for 204 clock cycles//
//***************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a0+a4+a5+a6,a4+a5+a3,a2+a3+a4,a1+a7+a2+a3,a1+a5+a2+a4,a1+a5+a6+a3,a2+a6+a7,a1+a5+a6+a7)
module syndcell_7(recword, clock, enable, hold, synvalue7);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue7;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^7
assign outmult[7] = (outreg[0] ^ outreg[4] ^ outreg[5] ^ outreg[6]);
assign outmult[6] = (outreg[3] ^ outreg[4] ^ outreg[5]);
assign outmult[5] = (outreg[3] ^ outreg[4] ^ outreg[2]);
assign outmult[4] = (outreg[1] ^outreg[2] ^ outreg[3] ^ outreg[7]);
assign outmult[3] = outreg[1]^outreg[2] ^ outreg[4] ^ outreg[5];
assign outmult[2] = (outreg[1] ^ outreg[3]^ outreg[5] ^ outreg[6]);
assign outmult[1] = (outreg[2] ^ outreg[6] ^ outreg[7]);
assign outmult[0] = (outreg[1] ^ outreg[5] ^ outreg[6] ^ outreg[7]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue7 = outreg;

endmodule

//***************************************************//
//syndcell_8 computes R(alpha^8) for 204 clock cycles//
//***************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a4+a5+a3,a2+a3+a4,a1+a7+a2+a3,a1+a2+a0+a6,,a1+a3+a0+a4,,a2+a7+a0+a4+a5,,a1+a5+a6+a7,a0+a4+a5+a6)

module syndcell_8(recword, clock, enable, hold, synvalue8);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue8;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^8
assign outmult[7] = (outreg[3] ^ outreg[4] ^ outreg[5]);
assign outmult[6] = (outreg[3] ^ outreg[4] ^ outreg[2]);
assign outmult[5] = (outreg[1] ^outreg[2] ^ outreg[3] ^ outreg[7]);
assign outmult[4] = outreg[1]^outreg[2] ^ outreg[0] ^ outreg[6];
assign outmult[3] = (outreg[0] ^ outreg[1]^ outreg[3] ^ outreg[4]);
assign outmult[2] = (outreg[0] ^ outreg[2]^ outreg[4] ^ outreg[5] ^ outreg[7]);
assign outmult[1] = (outreg[1] ^ outreg[5] ^ outreg[6] ^ outreg[7]);
assign outmult[0] = (outreg[0] ^ outreg[4] ^ outreg[5] ^ outreg[6]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue8 = outreg;

endmodule

//***************************************************//
//syndcell_9 computes R(alpha^9) for 204 clock cycles//
//***************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a2+a3+a4,a1+a7+a2+a3,a1+a2+a0+a6,,a1+a0+a5,,a2+a7+a0+a3,,a1+a6+a7+a4+a3,a0+a4+a5+a6,a4+a5+a3)

module syndcell_9(recword, clock, enable, hold, synvalue9);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue9;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^9
assign outmult[7] = (outreg[3] ^ outreg[4] ^ outreg[2]);
assign outmult[6] = (outreg[1] ^outreg[2] ^ outreg[3] ^ outreg[7]);
assign outmult[5] = outreg[1]^outreg[2] ^ outreg[0] ^ outreg[6];
assign outmult[4] = (outreg[0] ^ outreg[1]^ outreg[5]);
assign outmult[3] = (outreg[0] ^ outreg[2]^ outreg[3] ^ outreg[7]);
assign outmult[2] = (outreg[1] ^ outreg[3]^ outreg[4] ^ outreg[6] ^ outreg[7]);
assign outmult[1] = (outreg[0] ^ outreg[4] ^ outreg[5] ^ outreg[6]);
assign outmult[0] = (outreg[3] ^ outreg[4] ^ outreg[5]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue9 = outreg;

endmodule

//****************************************************//
//syndcell_10 computes R(alpha^10) for 204 clock cycles//
//****************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a1+a7+a2+a3,a1+a2+a0+a6,,a1+a0+a5,a7+a0+a4,,a1+a6+a7+a2,a0+a5+a6+a2+a3,,a4+a5+a3,a2+a3+a4,)

module syndcell_10(recword, clock, enable, hold, synvalue10);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue10;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^10
assign outmult[7] = (outreg[1] ^outreg[2] ^ outreg[3] ^ outreg[7]);
assign outmult[6] = outreg[1]^outreg[2] ^ outreg[0] ^ outreg[6];
assign outmult[5] = (outreg[0] ^ outreg[1]^ outreg[5]);
assign outmult[4] = (outreg[0] ^ outreg[4] ^ outreg[7]);
assign outmult[3] = (outreg[1] ^ outreg[2]^ outreg[6] ^ outreg[7]);
assign outmult[2] = (outreg[0] ^ outreg[2]^ outreg[3] ^ outreg[5] ^ outreg[6]);
assign outmult[1] = (outreg[3] ^ outreg[4] ^ outreg[5]);
assign outmult[0] = (outreg[3] ^ outreg[4] ^ outreg[2]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue10 = outreg;

endmodule

//****************************************************//
//syndcell_11 computes R(alpha^11) for 204 clock cycles//
//****************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a1+a2+a0+a6,,a1+a0+a5,a7+a0+a4,,a6+a3,a0+a5+a6+a1+a7,,a4+a5+a1+a7+a2,a2+a3+a4,a1+a7+a2+a3)

module syndcell_11(recword, clock, enable, hold, synvalue11);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue11;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^11

assign outmult[7] = outreg[1]^outreg[2] ^ outreg[0] ^ outreg[6];
assign outmult[6] = (outreg[0] ^ outreg[1]^ outreg[5]);
assign outmult[5] = (outreg[0] ^ outreg[4] ^ outreg[7]);
assign outmult[4] = (outreg[3] ^ outreg[6]);
assign outmult[3] = (outreg[0] ^ outreg[1]^ outreg[7] ^ outreg[5] ^ outreg[6]);
assign outmult[2] = (outreg[1]  ^outreg[2]^ outreg[4] ^ outreg[5]^ outreg[7]);
assign outmult[1] = (outreg[3] ^ outreg[4] ^ outreg[2]);
assign outmult[0] = (outreg[1] ^outreg[2] ^ outreg[3] ^ outreg[7]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue11 = outreg;

endmodule

//****************************************************//
//syndcell_12 computes R(alpha^12) for 204 clock cycles//
//****************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a1+a0+a5,a7+a0+a4,,a6+a3,a5+a7+a2,a4+a5+a7+a0+a6,a3+a4+a1+a0+a6,a1+a7+a2+a3,a1+a2+a0+a6)

module syndcell_12(recword, clock, enable, hold, synvalue12);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue12;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^12
assign outmult[7] = (outreg[0] ^ outreg[1]^ outreg[5]);
assign outmult[6] = (outreg[0] ^ outreg[4] ^ outreg[7]);
assign outmult[5] = (outreg[3] ^ outreg[6]);
assign outmult[4] = ( outreg[7] ^ outreg[5] ^ outreg[2]);
assign outmult[3] = (outreg[0]  ^outreg[6]^ outreg[4] ^ outreg[5]^ outreg[7]);
assign outmult[2] = (outreg[0] ^ outreg[1] ^ outreg[3]^ outreg[4] ^ outreg[6]);
assign outmult[1] = (outreg[1] ^outreg[2] ^ outreg[3] ^ outreg[7]);
assign outmult[0] = outreg[1]^outreg[2] ^ outreg[0] ^ outreg[6];

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue12 = outreg;

endmodule

//****************************************************//
//syndcell_13 computes R(alpha^13) for 204 clock cycles//
//****************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a7+a0+a4,,a6+a3,a5+a7+a2,a4+a7+a6+a1,a3+a4+a6+a5,a7+a2+a3+a0+a5,a1+a2+a0+a6,a1+a0+a5)

module syndcell_13(recword, clock, enable, hold, synvalue13);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue13;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^13
assign outmult[7] = (outreg[0] ^ outreg[4] ^ outreg[7]);
assign outmult[6] = (outreg[3] ^ outreg[6]);
assign outmult[5] = ( outreg[7] ^ outreg[5] ^ outreg[2]);
assign outmult[4] = (outreg[1]  ^outreg[6]^ outreg[4] ^ outreg[7]);
assign outmult[3] = (outreg[3] ^ outreg[5]^ outreg[4] ^ outreg[6]);
assign outmult[2] = (outreg[0] ^outreg[2] ^ outreg[3] ^ outreg[5]^ outreg[7]);
assign outmult[1] = outreg[1]^outreg[2] ^ outreg[0] ^ outreg[6];
assign outmult[0] = (outreg[0] ^ outreg[1]^ outreg[5]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue13 = outreg;

endmodule

//****************************************************//
//syndcell_14 computes R(alpha^14) for 204 clock cycles//
//****************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a6+a3,a5+a7+a2,a4+a7+a6+a1,a3+a6+a5+a7+a0,a2+a3+a5+a4,a1+a2+a6+a7+a4,a1+a0+a5,a7+a0+a4)

module syndcell_14(recword, clock, enable, hold, synvalue14);
input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue14;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^14
assign outmult[7] = (outreg[3] ^ outreg[6]);
assign outmult[6] = ( outreg[7] ^ outreg[5] ^ outreg[2]);
assign outmult[5] = (outreg[1]  ^outreg[6]^ outreg[4] ^ outreg[7]);
assign outmult[4] = (outreg[3] ^ outreg[5]^ outreg[0] ^ outreg[6]^ outreg[7]);
assign outmult[3] = (outreg[2] ^ outreg[3] ^ outreg[5]^ outreg[4]);
assign outmult[2] = outreg[1]^outreg[2] ^ outreg[4] ^ outreg[6]^ outreg[7];
assign outmult[1] = (outreg[0] ^ outreg[1]^ outreg[5]);
assign outmult[0] = (outreg[0] ^ outreg[4] ^ outreg[7]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue14 = outreg;

endmodule

//****************************************************//
//syndcell_15 computes R(alpha^15) for 204 clock cycles//
//****************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a6+a3,a5+a7+a2,a4+a7+a6+a1,a3+a6+a5+a7+a0,a2+a3+a5+a4,a1+a2+a6+a7+a4,a1+a0+a5,a7+a0+a4)
//     (a5+a7+a2,a4+a7+a6+a1,a3+a6+a5+a7+a0,a2+a5+a4+a6,a1+a2+a7+a4+a3,,a1+a0+a5+a6+a3,,a7+a0+a4,a6+a3)

module syndcell_15(recword, clock, enable, hold, synvalue15);
input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue15;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^15

assign outmult[7] = ( outreg[7] ^ outreg[5] ^ outreg[2]);
assign outmult[6] = (outreg[1]  ^outreg[6]^ outreg[4] ^ outreg[7]);
assign outmult[5] = (outreg[3] ^ outreg[5]^ outreg[0] ^ outreg[6]^ outreg[7]);
assign outmult[4] = (outreg[2] ^ outreg[6] ^ outreg[5]^ outreg[4]);
assign outmult[3] = outreg[1]^outreg[2] ^ outreg[4] ^ outreg[3]^ outreg[7];
assign outmult[2] = (outreg[0] ^ outreg[1]^ outreg[5]^outreg[3] ^ outreg[6]);
assign outmult[1] = (outreg[0] ^ outreg[4] ^ outreg[7]);
assign outmult[0] = (outreg[3] ^ outreg[6]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue15 = outreg;

endmodule