scblock.v

Reed-Solomon 信道编码广泛应用于DVB中

//*****************************************************************//
// Syndrome Computation                                            // 
// This block consists mainly of 12 cells. Each cell computes      //
// syndrome value Si, for i=0,...,11.                              //
// At the end of received word block, all cells store the syndrome //
// values, while SC block set its flag (errdetect) if one or more  //
// syndrome values are not zero.                                   //
// Ref.: "High-speed VLSI Architecture for Parallel Reed-Solomon   //
//        Decoder", IEEE Trans. on VLSI, April 2003.               //
//*****************************************************************//
module SCblock(recword, clock1, clock2, active_sc, reset, syndvalue0,syndvalue1,
               syndvalue2, syndvalue3, syndvalue4, syndvalue5, syndvalue6, syndvalue7,
             syndvalue8, syndvalue9, syndvalue10, syndvalue11, syndvalue12,
             syndvalue13,syndvalue14,syndvalue15,errdetect,  en_sccell, evalsynd, holdsynd);
input [7:0] recword;
input clock1, clock2, active_sc, reset, evalsynd, holdsynd, en_sccell;
output [7:0] syndvalue0, syndvalue1, syndvalue2, syndvalue3, syndvalue4, 
             syndvalue5, syndvalue6, syndvalue7, syndvalue8, syndvalue9, 
             syndvalue10, syndvalue11,syndvalue12,syndvalue13,syndvalue14,
             syndvalue15;
output errdetect;

reg errdetect;
reg [1:0] state, nxt_state;
parameter [1:0] st0=0, st1=1, st2=2;

always@(state or active_sc or evalsynd)
begin
    case(state)
        st0:   begin
               if(active_sc)
                  nxt_state <= st1;
               else
                  nxt_state <= st0;
               end
        st1:   begin
               if(evalsynd)
                  nxt_state <= st2;
               else
                  nxt_state <= st1;
               end
        st2:   nxt_state <= st0;
        default: nxt_state <= st0;
    endcase
end

always@(posedge clock2 or negedge reset)
begin
   if(~reset)
      state <= st0;
   else
      state <=  nxt_state;
end
 
always@(state or syndvalue0 or syndvalue1 or syndvalue2 or syndvalue3 or 
        syndvalue4 or syndvalue5 or syndvalue6 or syndvalue7 or syndvalue8 or
        syndvalue9 or syndvalue10 or syndvalue11 or syndvalue12 or
        syndvalue13 or syndvalue14 or syndvalue15)
begin
    case(state)
        st0:   errdetect <= 0;
        st1:   errdetect <= 0;
        st2:   begin
               if (syndvalue0 || syndvalue1 || syndvalue2 || syndvalue3 ||
                   syndvalue4 || syndvalue5 || syndvalue6 || syndvalue7 ||
                   syndvalue8 || syndvalue9 || syndvalue10 || syndvalue11||
                   syndvalue12 || syndvalue13 || syndvalue14 || syndvalue15)
                  errdetect <= 1;
               else
                  errdetect <= 0;
               end
        default:errdetect <= 0;
   endcase
end

syndcell_0 cell_0(recword, clock1, en_sccell, holdsynd, syndvalue0);
syndcell_1 cell_1(recword, clock1, en_sccell, holdsynd, syndvalue1);
syndcell_2 cell_2(recword, clock1, en_sccell, holdsynd, syndvalue2);
syndcell_3 cell_3(recword, clock1, en_sccell, holdsynd, syndvalue3);
syndcell_4 cell_4(recword, clock1, en_sccell, holdsynd, syndvalue4);
syndcell_5 cell_5(recword, clock1, en_sccell, holdsynd, syndvalue5);
syndcell_6 cell_6(recword, clock1, en_sccell, holdsynd, syndvalue6);
syndcell_7 cell_7(recword, clock1, en_sccell, holdsynd, syndvalue7);
syndcell_8 cell_8(recword, clock1, en_sccell, holdsynd, syndvalue8);
syndcell_9 cell_9(recword, clock1, en_sccell, holdsynd, syndvalue9);
syndcell_10 cell_10(recword, clock1, en_sccell, holdsynd, syndvalue10);
syndcell_11 cell_11(recword, clock1, en_sccell, holdsynd, syndvalue11);
syndcell_12 cell_12(recword, clock1, en_sccell, holdsynd, syndvalue12);
syndcell_13 cell_13(recword, clock1, en_sccell, holdsynd, syndvalue13);
syndcell_14 cell_14(recword, clock1, en_sccell, holdsynd, syndvalue14);
syndcell_15 cell_15(recword, clock1, en_sccell, holdsynd, syndvalue15);

endmodule    


//*****************************/
// Syndrome Computation Cells //
//****************************//

//**************************************************//
//syndcell_0 computes R(alpha^0) for 204 clock cycles//
//**************************************************//
module syndcell_0(recword, clock, enable, hold, synvalue0);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue0;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^0
assign outmult = outreg;

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue0 = outreg;

endmodule

//**************************************************//
//syndcell_1 computes R(alpha^1) for 204 clock cycles//
//**************************************************//
module syndcell_1(recword, clock, enable, hold, synvalue1);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue1;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^1
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a6,a5,a4,a3+a7,a2+a7,a1+a7,a0,a7) 
assign outmult[0] = outreg[7];
assign outmult[1] = outreg[0];
assign outmult[2] = outreg[1] ^ outreg[7];
assign outmult[3] = outreg[2] ^ outreg[7];
assign outmult[4] = outreg[3] ^ outreg[7];
assign outmult[5] = outreg[4];
assign outmult[6] = outreg[5];
assign outmult[7] = outreg[6];

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue1 = outreg;

endmodule

//**************************************************//
//syndcell_2 computes R(alpha^2) for 204 clock cycles//
//**************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a5,a4,a3+a7,a2+a6+a7,a1+a6+a7,a0+a6,a7,a6) 
module syndcell_2(recword, clock, enable, hold, synvalue2);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue2;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^2
assign outmult[0] = outreg[6];
assign outmult[1] = outreg[7];
assign outmult[2] = (outreg[0] ^ outreg[6]);
assign outmult[3] = (outreg[6] ^ outreg[7]) ^ outreg[1];
assign outmult[4] = outreg[2]^ (outreg[6] ^ outreg[7]);
assign outmult[5] = outreg[3]^ outreg[7];
assign outmult[6] = outreg[4];
assign outmult[7] = outreg[5];

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue2 = outreg;

endmodule

//**************************************************//
//syndcell_3 computes R(alpha^3) for 204 clock cycles//
//**************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a4,a3+a7,a2+a6+a7,a1+a5+a6+a7,a0+a5+a6,a5+a7,a6,a5) 
module syndcell_3(recword, clock, enable, hold, synvalue3);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue3;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^3
assign outmult[0] = outreg[5];
assign outmult[1] = outreg[6];
assign outmult[2] = outreg[5] ^ outreg[7];
assign outmult[3] = outreg[0] ^ outreg[5]^ outreg[6];
assign outmult[4] = (outreg[1] ^ outreg[7]) ^ (outreg[5] ^ outreg[6]);
assign outmult[5] = outreg[2] ^ outreg[6]^ outreg[7];
assign outmult[6] = outreg[3] ^ outreg[7];
assign outmult[7] = outreg[4];

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue3 = outreg;

endmodule

//***************************************************//
//syndcell_4 computes R(alpha^4) for 204 clock cycles//
//**************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a3+a7,a2+a6+a7,a1+a5+a6+a7,a0+a4+a5+a6,a4+a5+a7,a4+a6,a5,a4)
module syndcell_4(recword, clock, enable, hold, synvalue4);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue4;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^4
assign outmult[7] = (outreg[3] ^ outreg[7]);
assign outmult[6] = (outreg[2] ^ outreg[6] ^ outreg[7]);
assign outmult[5] = (outreg[1] ^ outreg[5] ^ outreg[6] ^ outreg[7]);
assign outmult[4] = (outreg[0] ^ outreg[4] ^ outreg[5] ^ outreg[6]);
assign outmult[3] = (outreg[4] ^ outreg[5] ^ outreg[7]);
assign outmult[2] = (outreg[4] ^ outreg[6]);
assign outmult[1] = outreg[5];
assign outmult[0] = outreg[4];

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue4 = outreg;

endmodule

//***************************************************//
//syndcell_5 computes R(alpha^5) for 204 clock cycles//
//***************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a2+a6+a7,a1+a5+a6+a7,a0+a4+a5+a6,a4+a5+a3,a3+a7+a4+a6,a3+a7+a5,a4,a3+a7)
module syndcell_5(recword, clock, enable, hold, synvalue5);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue5;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^5
assign outmult[7] = (outreg[2] ^ outreg[6] ^ outreg[7]);
assign outmult[6] = (outreg[1] ^ outreg[5] ^ outreg[6] ^ outreg[7]);
assign outmult[5] = (outreg[0] ^ outreg[4] ^ outreg[5] ^ outreg[6]);
assign outmult[4] = (outreg[3] ^ outreg[4] ^ outreg[5]);
assign outmult[3] = (outreg[3] ^ outreg[4] ^ outreg[6] ^ outreg[7]);
assign outmult[2] = (outreg[3] ^ outreg[5] ^ outreg[7]);
assign outmult[1] = outreg[4];
assign outmult[0] = (outreg[3] ^ outreg[7]);

register8_wlh register8bit(outadder, outreg, enable, hold, clock);
gfadder   adder(recword, outmult, outadder);
assign synvalue5 = outreg;

endmodule

//***************************************************//
//syndcell_6 computes R(alpha^6) for 204 clock cycles//
//***************************************************//
//alpha(a7,a6,a5,a4,a3,a2,a1,a0)->
//     (a1+a5+a6+a7,a0+a4+a5+a6,a4+a5+a3,a2+a3+a4,a2+a6+a3+a5,a2+a6+a7+a4,a3+a7,a2+a6+a7)
module syndcell_6(recword, clock, enable, hold, synvalue6);

input [7:0] recword;
input clock;
input enable, hold;
output [7:0] synvalue6;

wire [7:0] outreg;
wire [7:0] outadder;
wire [7:0] outmult;

//multiply recword with constant alpha^6

assign outmult[7] = (outreg[1] ^ outreg[5] ^ outreg[6] ^ outreg[7]);
assign outmult[6] = (outreg[0] ^ outreg[4] ^ outreg[5] ^ outreg[6]);
assign outmult[5] = (outreg[3] ^ outreg[4] ^ outreg[5]);
assign outmult[4] = (outreg[3] ^ outreg[4] ^ outreg[2]);
assign outmult[3] = (outreg[2] ^outreg[3] ^ outreg[5] ^ outreg[6]);
assign outmult[2] = outreg[4]^outreg[2] ^ outreg[6] ^ outreg[7];