rsdecoder.srr

Reed-Solomon 信道编码广泛应用于DVB中

Automatic dissolve at startup in view:work.PE(verilog) of reg2(register_pe)
Automatic dissolve at startup in view:work.PE(verilog) of reg1(register_pe)
Automatic dissolve at startup in view:work.PE_16(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.PE_16(verilog) of reg2(register_pe_reg2)
Automatic dissolve at startup in view:work.PE_16(verilog) of reg1(register_pe_reg1)
Automatic dissolve at startup in view:work.PE_24(verilog) of multiplexer(mux2_to_1_multiplexer)
Automatic dissolve at startup in view:work.PE_24(verilog) of reg2(register_pe_reg2_1)
Automatic dissolve at startup in view:work.PE_24(verilog) of reg1(register_pe_reg1_1)
Automatic dissolve at startup in view:work.control(verilog) of regkr(regkr)
Automatic dissolve at startup in view:work.control(verilog) of reggamma(regamma)
Automatic dissolve at startup in view:work.control(verilog) of multiplexer2(mux2_to_1)
Automatic dissolve at startup in view:work.control(verilog) of multiplexer1(mux2_to_1)
Automatic dissolve at startup in view:work.KES_block(verilog) of pencoder(priority_encoder)
Automatic dissolve at startup in view:work.degree0_cell(verilog) of multiplex(mux2_to_1)
Automatic dissolve at startup in view:work.degree0_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree1_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree1_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree2_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree2_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree3_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree3_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree4_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree4_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree5_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree5_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree6_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree6_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree7_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree7_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree8_cell(verilog) of multiplexer(mux2_to_1)
Automatic dissolve at startup in view:work.degree8_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.degree16_cell(verilog) of multiplexer(mux2_to_1_multiplexer_1)
Automatic dissolve at startup in view:work.degree16_cell(verilog) of register(register8_wl)
Automatic dissolve at startup in view:work.CSEEblock(verilog) of erroreg(register8_wl)
Automatic dissolve at startup in view:work.CSEEblock(verilog) of fn0_cell(degree0_cell)
Automatic dissolve at startup in view:work.CSEEblock(verilog) of cs0_cell(degree0_cell)
Automatic dissolve at startup in view:work.RSDecoder(verilog) of fiforeg(fifo_register)
Encoding state machine work.SCblock(verilog)-state[2:0]
original code -> new code
   00 -> 00
   01 -> 01
   10 -> 10
Encoding state machine work.control(verilog)-state[4:0]
original code -> new code
   000 -> 00001
   001 -> 00010
   010 -> 00100
   011 -> 01000
   100 -> 10000
@N:"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":144:0:144:5|Found counter in view:work.control(verilog) inst cntr[4:0]
Encoding state machine work.MainControl(verilog)-state1[16:0]
original code -> new code
   00000 -> 00000000000000001
   00001 -> 00000000000000010
   00010 -> 00000000000000100
   00011 -> 00000000000001000
   00100 -> 00000000000010000
   00101 -> 00000000000100000
   00110 -> 00000000001000000
   00111 -> 00000000010000000
   01000 -> 00000000100000000
   01001 -> 00000001000000000
   01010 -> 00000010000000000
   01011 -> 00000100000000000
   01100 -> 00001000000000000
   01101 -> 00010000000000000
   01110 -> 00100000000000000
   01111 -> 01000000000000000
   10000 -> 10000000000000000
Encoding state machine work.MainControl(verilog)-state2[11:0]
original code -> new code
   0000 -> 000000000001
   0001 -> 000000000010
   0010 -> 000000000100
   0011 -> 000000001000
   0100 -> 000000010000
   0101 -> 000000100000
   0110 -> 000001000000
   0111 -> 000010000000
   1000 -> 000100000000
   1001 -> 001000000000
   1010 -> 010000000000
   1011 -> 100000000000
@N:"f:\servu\zhaojia\rs\code version1\sourcecode\maincontrol\controller.v":620:0:620:5|Found counter in view:work.MainControl(verilog) inst cntdatain[7:0]
@N:"f:\servu\zhaojia\rs\code version1\sourcecode\maincontrol\controller.v":611:0:611:5|Found counter in view:work.MainControl(verilog) inst cntdataout[7:0]
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_15(syndcell_15)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_14(syndcell_14)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_13(syndcell_13)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_12(syndcell_12)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_11(syndcell_11)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_10(syndcell_10)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_9(syndcell_9)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_8(syndcell_8)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_7(syndcell_7)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_6(syndcell_6)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_5(syndcell_5)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_4(syndcell_4)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_3(syndcell_3)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_2(syndcell_2)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_1(syndcell_1)
Automatic dissolve during optimization of view:work.SCblock(verilog) of cell_0(syndcell_0)
Automatic dissolve during optimization of view:work.control(verilog) of adder(fulladder)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of invers(inverscomb)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of patch_cell(degree16_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn7_cell(degree7_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn6_cell(degree6_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn5_cell(degree5_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn4_cell(degree4_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn3_cell(degree3_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn2_cell(degree2_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fn1_cell(degree1_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fnpre6(degree51_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fnpre4(degree204_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fnpre3(degree153_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of fnpre1(degree51_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs8_cell(degree8_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs7_cell(degree7_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs6_cell(degree6_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs5_cell(degree5_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs4_cell(degree4_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs3_cell(degree3_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs2_cell(degree2_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cs1_cell(degree1_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cspre8(degree153_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cspre6(degree51_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cspre4(degree204_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cspre3(degree153_cell)
Automatic dissolve during optimization of view:work.CSEEblock(verilog) of cspre1(degree51_cell)
Auto Dissolve of KESblock (inst of view:work.KES_block(verilog))

Clock Buffers:
  Inserting Clock buffer for port clock1,	TNM=clock1
  Inserting Clock buffer for port clock2,	TNM=clock2

@W: BN132 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing instance KESblock.PE24.reg2.dataout[6],  because it is equivalent to instance KESblock.PE24.reg2.dataout[7]
@W: BN132 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing instance KESblock.PE24.reg2.dataout[5],  because it is equivalent to instance KESblock.PE24.reg2.dataout[7]
@W: BN132 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing instance KESblock.PE24.reg2.dataout[4],  because it is equivalent to instance KESblock.PE24.reg2.dataout[7]
@W: BN132 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing instance KESblock.PE24.reg2.dataout[3],  because it is equivalent to instance KESblock.PE24.reg2.dataout[7]
@W: BN132 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing instance KESblock.PE24.reg2.dataout[2],  because it is equivalent to instance KESblock.PE24.reg2.dataout[7]
@W: BN132 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing instance KESblock.PE24.reg2.dataout[1],  because it is equivalent to instance KESblock.PE24.reg2.dataout[7]
@W: BN116 :"f:\servu\zhaojia\rs\code version1\sourcecode\kes_block\kes.v":458:0:458:5|Removing sequential instance KESblock.PE24.reg2.dataout[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: MT204 |Autoconstrain Mode is ON
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:1m:50s		    -1.62ns		4670 /       755
   2		0h:1m:51s		    -1.35ns		4673 /       755
   3		0h:1m:52s		    -1.16ns		4696 /       755
   4		0h:1m:54s		    -1.14ns		4717 /       755
   5		0h:2m:2s		    -1.14ns		4893 /       755
   6		0h:2m:4s		    -1.14ns		4893 /       755
   7		0h:2m:4s		    -1.14ns		4893 /       755