rsdecoder.srr

Reed-Solomon 信道编码广泛应用于DVB中

$ Start of Compile
#Fri Sep 07 15:33:54 2007

Synplicity Verilog Compiler, version Compilers 2.8.1, Build 015R, built Sep  2 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved

@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\COMMON_MODULES\common_modules.v"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\CSEE_block\cseeblock.v"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\SCBLOCK\SCBLOCK.V"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\Fifo\asyncfifo256.v"
@N:"F:\ServU\zhaojia\RS\code version1\SourceCode\Fifo\asyncfifo256.v":62:12:62:24|Read directive translate_off 
@N:"F:\ServU\zhaojia\RS\code version1\SourceCode\Fifo\asyncfifo256.v":147:12:147:23|Read directive translate_on 
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\Fifo\FIFO_GENERATOR_V2_0.v"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\Fifo\fifo_register.v"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\KES_block\kes.v"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\MainControl\controller.v"
@I::"F:\ServU\zhaojia\RS\code version1\SourceCode\RS_Decoder_Top\RSDecoder.v"
Verilog syntax check successful!
Options changed - recompiling
Selecting top level module RSDecoder
Synthesizing module register8_wlh
@N: CG179 :"F:\ServU\zhaojia\RS\code version1\SourceCode\COMMON_MODULES\common_modules.v":18:14:18:16|Removing redundant assignment
Synthesizing module gfadder
Synthesizing module syndcell_0
Synthesizing module syndcell_1
Synthesizing module syndcell_2
Synthesizing module syndcell_3
Synthesizing module syndcell_4
Synthesizing module syndcell_5
Synthesizing module syndcell_6
Synthesizing module syndcell_7
Synthesizing module syndcell_8
Synthesizing module syndcell_9
Synthesizing module syndcell_10
Synthesizing module syndcell_11
Synthesizing module syndcell_12
Synthesizing module syndcell_13
Synthesizing module syndcell_14
Synthesizing module syndcell_15
Synthesizing module SCblock
@N: CL201 :"F:\ServU\zhaojia\RS\code version1\SourceCode\SCBLOCK\SCBLOCK.V":47:0:47:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
Synthesizing module lcpmult
Synthesizing module register_pe
@N: CG179 :"F:\ServU\zhaojia\RS\code version1\SourceCode\KES_block\kes.v":465:14:465:16|Removing redundant assignment
Synthesizing module mux2_to_1
Synthesizing module PE
Synthesizing module PE_16
Synthesizing module PE_24
Synthesizing module fulladder
Synthesizing module regamma
Synthesizing module regkr
Synthesizing module control
@N: CL201 :"F:\ServU\zhaojia\RS\code version1\SourceCode\KES_block\kes.v":182:0:182:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
Synthesizing module priority_encoder
Synthesizing module KES_block
Synthesizing module degree51_cell
Synthesizing module degree102_cell
Synthesizing module degree153_cell
Synthesizing module degree204_cell
Synthesizing module register8_wl
Synthesizing module degree0_cell
Synthesizing module degree1_cell
Synthesizing module degree2_cell
Synthesizing module degree3_cell
Synthesizing module degree4_cell
Synthesizing module degree5_cell
Synthesizing module degree6_cell
Synthesizing module degree7_cell
Synthesizing module degree8_cell
Synthesizing module degree16_cell
Synthesizing module inverscomb
Synthesizing module CSEEblock
@N: CG179 :"F:\ServU\zhaojia\RS\code version1\SourceCode\CSEE_block\cseeblock.v":103:22:103:29|Removing redundant assignment
Synthesizing module MainControl
@N: CG179 :"F:\ServU\zhaojia\RS\code version1\SourceCode\MainControl\controller.v":635:24:635:40|Removing redundant assignment
@N: CL201 :"F:\ServU\zhaojia\RS\code version1\SourceCode\MainControl\controller.v":381:0:381:5|Trying to extract state machine for register state2
Extracted state machine for register state2
State machine has 12 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
   1010
   1011
@N: CL201 :"F:\ServU\zhaojia\RS\code version1\SourceCode\MainControl\controller.v":59:0:59:5|Trying to extract state machine for register state1
Extracted state machine for register state1
State machine has 17 reachable states with original encodings of:
   00000
   00001
   00010
   00011
   00100
   00101
   00110
   00111
   01000
   01001
   01010
   01011
   01100
   01101
   01110
   01111
   10000
Synthesizing module asyncfifo256
@W: CG146 :"F:\ServU\zhaojia\RS\code version1\SourceCode\Fifo\asyncfifo256.v":40:7:40:18|Creating black box for empty module asyncfifo256

Synthesizing module fifo_register
Synthesizing module RSDecoder
@END
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
###########################################################[
Synplicity Xilinx Technology Mapper, version 7.7.0, Build 033R, built Sep  9 2004
Copyright (C) 1994-2004, Synplicity Inc.  All Rights Reserved


Automatic dissolve at startup in view:work.syndcell_0(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_1(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_2(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_3(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_4(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_5(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_6(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_7(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_8(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_9(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_10(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_11(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_12(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_13(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_14(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.syndcell_15(verilog) of register8bit(register8_wlh)
Automatic dissolve at startup in view:work.PE(verilog) of multiplexer(mux2_to_1)