proj_1.prj

Reed-Solomon 信道编码广泛应用于DVB中

#-- Synplicity, Inc.
#-- Version 7.7       
#-- Project file F:\ServU\zhaojia\RS\code version1\Synplify Pro\RsDecoder\proj_1.prj
#-- Written on Wed Sep 05 18:44:27 2007


#add_file options
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/COMMON_MODULES/common_modules.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/SCBLOCK/SCBLOCK.V"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/Fifo/asyncfifo256.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/Fifo/FIFO_GENERATOR_V2_0.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/Fifo/fifo_register.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/CSEE_block/cseeblock.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/KES_block/kes.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/MainControl/controller.v"
add_file -verilog "F:/ServU/zhaojia/RS/code version1/verilog code/RS_Decoder_Top/RSDecoder.v"


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology VIRTEX4
set_option -part XC4VLX15
set_option -package SF363
set_option -speed_grade -10

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency auto
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/RSDecoder.edf"

#implementation attributes
set_option -vlog_std v2001
set_option -auto_constrain_io 0
impl -active "rev_1"