_primary.vhd

Reed-Solomon 信道编码广泛应用于DVB中

library verilog;
use verilog.vl_types.all;
entity syndcell_2 is
    port(
        recword         : in     vl_logic_vector(0 to 4);
        clock           : in     vl_logic;
        enable          : in     vl_logic;
        hold            : in     vl_logic;
        synvalue2       : out    vl_logic_vector(0 to 4)
    );
end syndcell_2;