_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 12 行

library verilog;
use verilog.vl_types.all;
entity regamma is
    port(
        datain          : in     vl_logic_vector(4 downto 0);
        dataout         : out    vl_logic_vector(4 downto 0);
        load            : in     vl_logic;
        initialize      : in     vl_logic;
        clock           : in     vl_logic
    );
end regamma;