_primary.vhd

来自「Reed-Solomon 信道编码广泛应用于DVB中」· VHDL 代码 · 共 38 行

library verilog;
use verilog.vl_types.all;
entity KES_block is
    port(
        active_kes      : in     vl_logic;
        clock1          : in     vl_logic;
        clock2          : in     vl_logic;
        reset           : in     vl_logic;
        syndvalue0      : in     vl_logic_vector(4 downto 0);
        syndvalue1      : in     vl_logic_vector(4 downto 0);
        syndvalue2      : in     vl_logic_vector(4 downto 0);
        syndvalue3      : in     vl_logic_vector(4 downto 0);
        syndvalue4      : in     vl_logic_vector(4 downto 0);
        syndvalue5      : in     vl_logic_vector(4 downto 0);
        syndvalue6      : in     vl_logic_vector(4 downto 0);
        syndvalue7      : in     vl_logic_vector(4 downto 0);
        syndvalue8      : in     vl_logic_vector(4 downto 0);
        syndvalue9      : in     vl_logic_vector(4 downto 0);
        syndvalue10     : in     vl_logic_vector(4 downto 0);
        syndvalue11     : in     vl_logic_vector(4 downto 0);
        lambda0         : out    vl_logic_vector(4 downto 0);
        lambda1         : out    vl_logic_vector(4 downto 0);
        lambda2         : out    vl_logic_vector(4 downto 0);
        lambda3         : out    vl_logic_vector(4 downto 0);
        lambda4         : out    vl_logic_vector(4 downto 0);
        lambda5         : out    vl_logic_vector(4 downto 0);
        lambda6         : out    vl_logic_vector(4 downto 0);
        homega0         : out    vl_logic_vector(4 downto 0);
        homega1         : out    vl_logic_vector(4 downto 0);
        homega2         : out    vl_logic_vector(4 downto 0);
        homega3         : out    vl_logic_vector(4 downto 0);
        homega4         : out    vl_logic_vector(4 downto 0);
        homega5         : out    vl_logic_vector(4 downto 0);
        lambda_degree   : out    vl_logic_vector(2 downto 0);
        finish          : out    vl_logic
    );
end KES_block;