idct_ia64_ecc.s

wince下的xvidcore开发库,可用于MP4等视频播放开发

addreg1 = r14                                                             
addreg2 = r15                                                             
c0 = f32                                                                  
c1 = f33                                                                  
c2 = f34                                                                  
c3 = f35                                                                  
c4 = f36                                                                  
c5 = f37                                                                  
c6 = f38                                                                  
c7 = f39                                                                  
c8 = f40                                                                  
c9 = f41                                                                  
c10 = f42                                                                 
c11 = f43                                                                 
c12 = f44                                                                 
c13 = f45                                                                 
c14 = f46                                                                 
c15 = f47                                                                 
.sdata                                                                    
.align 16                                                                 
.data_c0:                                                                 
real4 0.353553390593273730857504233427, 0.353553390593273730857504233427  
.data_c1:                                                                 
real4 -2.414213562373094923430016933708, -2.414213562373094923430016933708
.align 16                                                                 
.data_c2:                                                                 
real4 -0.414213562373095034452319396223, -0.414213562373095034452319396223
.data_c3:                                                                 
real4 0.198912367379658006072418174881, 0.198912367379658006072418174881  
.align 16                                                                 
.data_c4:                                                                 
real4 5.027339492125848074977056967327, 5.027339492125848074977056967327  
.data_c5:                                                                 
real4 0.668178637919298878955487452913, 0.668178637919298878955487452913  
.align 16                                                                 
.data_c6:                                                                 
real4 1.496605762665489169904731170391, 1.496605762665489169904731170391  
.data_c7:                                                                 
real4 0.461939766255643369241568052530, 0.461939766255643369241568052530  
.align 16                                                                 
.data_c8:                                                                 
real4 0.191341716182544890889616340246, 0.191341716182544890889616340246  
.data_c9:                                                                 
real4 0.847759065022573476966272210120, 0.847759065022573476966272210120  
.align 16                                                                 
.data_c10:                                                                
real4 2.847759065022573476966272210120, 2.847759065022573476966272210120  
.data_c11:                                                                
real4 5.027339492125848074977056967327, 5.027339492125848074977056967327  
.align 16                                                                 
.data_c12:                                                                
real4 0.490392640201615215289621119155, 0.490392640201615215289621119155  
.data_c13:                                                                
real4 0.068974844820735750627882509889, 0.068974844820735750627882509889  
.align 16                                                                 
.data_c14:                                                                
real4 0.097545161008064124041894160655, 0.097545161008064124041894160655  
.data_c15:                                                                
real4 1.000000000000000000000000000000, 1.000000000000000000000000000000  
                                                                          
.text                                                                     
.global idct_ia64                                                         
.global idct_ia64_init                                                    
.align 16                                                                 
.proc idct_ia64_init                                                      
idct_ia64_init:                                                           
br.ret.sptk.few b0                                                        
.endp                                                                     
.align 16                                                                 
.proc idct_ia64                                                           
idct_ia64:                                                                
                                                                          
        addreg3 = r20                                                     
        addreg4 = r21                                                     
        addreg5 = r22                                                     
        addreg6 = r23                                                     
                                                                          
        one = f30                                                         
        alloc   r16 = ar.pfs, 1, 71, 0, 0                                 
        addl    addreg1 = @gprel(.data_c0#), gp                           
        addl    addreg2 = @gprel(.data_c2#), gp                           
        ;;                                                                
        add     addreg3 = 32, addreg1                                     
        add     addreg4 = 32, addreg2                                     
        add     addreg5 = 64, addreg1                                     
        add     addreg6 = 64, addreg2                                     
        ;;                                                                
        ldfp8   c0, c1 = [addreg1]                                        
        ldfp8   c2, c3 = [addreg2]                                        
        ;;                                                                
        ldfp8   c4, c5 = [addreg3], 16                                    
        ldfp8   c6, c7 = [addreg4], 16                                    
        add     addreg1 = 96, addreg1                                     
        add     addreg2 = 96, addreg2                                     
        ;;                                                                
        ldfp8   c8, c9 = [addreg5], 16                                    
        ldfp8   c10, c11 = [addreg6], 16                                  
        ;;                                                                
        ldfp8   c12, c13 = [addreg1]                                      
        ldfp8   c14, c15 = [addreg2]                                      
        ;;                                                                
        mov     addreg1 = in0                                             
        fpack   one = f1, f1                                              
        add     addreg2 = 2, in0                                          
        ;;                                                                
                                                                          
        ld2  r33 = [addreg1], 4                                           
        ld2  r34 = [addreg2], 4                                           
        ;;                                                                
        ld2  r35 = [addreg1], 4                                           
        ld2  r36 = [addreg2], 4                                           
        ;;                                                                
        ld2  r37 = [addreg1], 4                                           
        ld2  r38 = [addreg2], 4                                           
        ;;                                                                
        ld2  r39 = [addreg1], 4                                           
        ld2  r40 = [addreg2], 4                                           
        ;;                                                                
        ld2  r41 = [addreg1], 4                                           
        ld2  r42 = [addreg2], 4                                           
        ;;                                                                
        ld2  r43 = [addreg1], 4                                           
        ld2  r44 = [addreg2], 4                                           
        ;;                                                                
        ld2  r45 = [addreg1], 4                                           
        ld2  r46 = [addreg2], 4                                           
        ;;                                                                
        ld2  r47 = [addreg1], 4                                           
        ld2  r48 = [addreg2], 4                                           
        ;;                                                                
        ld2  r49 = [addreg1], 4                                           
        ld2  r50 = [addreg2], 4                                           
        ;;                                                                
        ld2  r51 = [addreg1], 4                                           
        ld2  r52 = [addreg2], 4                                           
        ;;                                                                
        ld2  r53 = [addreg1], 4                                           
        ld2  r54 = [addreg2], 4                                           
        ;;                                                                
        ld2  r55 = [addreg1], 4                                           
        ld2  r56 = [addreg2], 4                                           
        ;;                                                                
        ld2  r57 = [addreg1], 4                                           
        ld2  r58 = [addreg2], 4                                           
        ;;                                                                
        ld2  r59 = [addreg1], 4                                           
        ld2  r60 = [addreg2], 4                                           
        ;;                                                                
        ld2  r61 = [addreg1], 4                                           
        ld2  r62 = [addreg2], 4                                           
        ;;                                                                
        ld2  r63 = [addreg1], 4                                           
        ld2  r64 = [addreg2], 4                                           
        ;;                                                                
        ld2  r65 = [addreg1], 4                                           
        ld2  r66 = [addreg2], 4                                           
        ;;                                                                
        ld2  r67 = [addreg1], 4                                           
        ld2  r68 = [addreg2], 4                                           
        ;;                                                                
        ld2  r69 = [addreg1], 4                                           
        ld2  r70 = [addreg2], 4                                           
        ;;                                                                
        ld2  r71 = [addreg1], 4                                           
        ld2  r72 = [addreg2], 4                                           
        ;;                                                                
        ld2  r73 = [addreg1], 4                                           
        ld2  r74 = [addreg2], 4                                           
        ;;                                                                
        ld2  r75 = [addreg1], 4                                           
        ld2  r76 = [addreg2], 4                                           
        ;;                                                                
        ld2  r77 = [addreg1], 4