idct_3dne.asm

wince下的xvidcore开发库,可用于MP4等视频播放开发

 ;/****************************************************************************
 ; *
 ; *  XVID MPEG-4 VIDEO CODEC
 ; *  - MMX and XMM forward discrete cosine transform -
 ; *
 ; *  Copyright(C) 2001 Peter Ross <[e-mail]>
 ; *               2002 Jaan Kalda
 ; *
 ; *  This program is free software; you can redistribute it and/or modify it
 ; *  under the terms of the GNU General Public License as published by
 ; *  the Free Software Foundation; either version 2 of the License, or
 ; *  (at your option) any later version.
 ; *
 ; *  This program is distributed in the hope that it will be useful,
 ; *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 ; *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 ; *  GNU General Public License for more details.
 ; *
 ; *  You should have received a copy of the GNU General Public License
 ; *  along with this program; if not, write to the Free Software
 ; *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
 ; *
 ; * $Id: idct_3dne.asm,v 1.1 2005/07/21 09:08:25 klschoef Exp $
 ; *
 ; ***************************************************************************/
 
 ; ****************************************************************************
 ;
 ; Originally provided by Intel at AP-922
 ; http://developer.intel.com/vtune/cbts/strmsimd/922down.htm
 ; (See more app notes at http://developer.intel.com/vtune/cbts/strmsimd/appnotes.htm)
 ; but in a limited edition.
 ; New macro implements a column part for precise iDCT
 ; The routine precision now satisfies IEEE standard 1180-1990.
 ;
 ; Copyright(C) 2000-2001 Peter Gubanov <[e-mail]>
 ; Rounding trick Copyright(C) 2000 Michel Lespinasse <[e-mail]>
 ;
 ; http://www.elecard.com/peter/idct.html
 ; http://www.linuxvideo.org/mpeg2dec/
 ;
 ; ***************************************************************************/
 ;
 ; These examples contain code fragments for first stage iDCT 8x8
 ; (for rows) and first stage DCT 8x8 (for columns)
 ;
 
 ; ***************************************************************************/
 ; this 3dne function is compatible with iSSE, but is optimized specifically for
 ; K7 pipelines (ca 5% gain), for implementation details see the idct_mmx.asm
 ; file
 ;
 ; ----------------------------------------------------------------------------
 ; Athlon optimizations contributed by Jaan Kalda
 ;-----------------------------------------------------------------------------
 
 BITS 32
 
 ;=============================================================================
 ; Macros and other preprocessor constants
 ;=============================================================================
 
 %macro cglobal 1
         %ifdef PREFIX
                 global _%1
                 %define %1 _%1
         %else
                 global %1
         %endif
 %endmacro
 
 %define BITS_INV_ACC    5                         ; 4 or 5 for IEEE
 %define SHIFT_INV_ROW   16 - BITS_INV_ACC
 %define SHIFT_INV_COL   1 + BITS_INV_ACC
 %define RND_INV_ROW     1024 * (6 - BITS_INV_ACC) ; 1 << (SHIFT_INV_ROW-1)
 %define RND_INV_COL     16 * (BITS_INV_ACC - 3)   ; 1 << (SHIFT_INV_COL-1)
 %define RND_INV_CORR    RND_INV_COL - 1           ; correction -1.0 and round
 
 %define BITS_FRW_ACC    3                         ; 2 or 3 for accuracy
 %define SHIFT_FRW_COL   BITS_FRW_ACC
 %define SHIFT_FRW_ROW   BITS_FRW_ACC + 17
 %define RND_FRW_ROW     262144*(BITS_FRW_ACC - 1) ; 1 << (SHIFT_FRW_ROW-1)
 
 ;=============================================================================
 ; Local Data (Read Only)
 ;=============================================================================
 
 %ifdef FORMAT_COFF
 SECTION .rodata data
 %else
 SECTION .rodata data align=16
 %endif
 
 ;-----------------------------------------------------------------------------
 ; Various memory constants (trigonometric values or rounding values)
 ;-----------------------------------------------------------------------------
 
 ALIGN 16
 one_corr:
   dw 1, 1, 1, 1
 round_inv_row:
   dd RND_INV_ROW,  RND_INV_ROW
 round_inv_col:
   dw RND_INV_COL,  RND_INV_COL,  RND_INV_COL, RND_INV_COL
 round_inv_corr:
   dw RND_INV_CORR, RND_INV_CORR, RND_INV_CORR, RND_INV_CORR
 round_frw_row:
   dd RND_FRW_ROW,  RND_FRW_ROW
 tg_1_16:
   dw 13036,  13036,  13036,  13036     ; tg * (2<<16) + 0.5
 tg_2_16:
   dw 27146,  27146,  27146,  27146     ; tg * (2<<16) + 0.5
 tg_3_16:
   dw -21746, -21746, -21746, -21746    ; tg * (2<<16) + 0.5
 cos_4_16:
   dw -19195, -19195, -19195, -19195    ; cos * (2<<16) + 0.5
 ocos_4_16:
   dw 23170,  23170,  23170,  23170     ; cos * (2<<15) + 0.5
 otg_3_16:
   dw 21895, 21895, 21895, 21895        ; tg * (2<<16) + 0.5
 
 %if SHIFT_INV_ROW == 12   ; assume SHIFT_INV_ROW == 12
 rounder_0:
   dd 65536, 65536
 rounder_4:
   dd 0, 0
 rounder_1:
   dd 7195, 7195
 rounder_7
   dd 1024, 1024
 rounder_2:
   dd 4520, 4520
 rounder_6:
   dd 1024, 1024
 rounder_3:
   dd 2407, 2407
 rounder_5:
   dd 240, 240
 
 %elif SHIFT_INV_ROW == 11   ; assume SHIFT_INV_ROW == 11
 rounder_0:
   dd 65536, 65536
 rounder_4:
   dd 0, 0
 rounder_1:
   dd 3597, 3597
 rounder_7:
   dd 512, 512
 rounder_2:
   dd 2260, 2260
 rounder_6:
   dd 512, 512
 rounder_3:
   dd 1203, 1203
 rounder_5:
   dd 120, 120
 %else
 
 %error invalid SHIFT_INV_ROW
 
 %endif
 
 ;-----------------------------------------------------------------------------
 ; Tables for xmm processors
 ;-----------------------------------------------------------------------------
 
 ; %3 for rows 0,4 - constants are multiplied by cos_4_16
 tab_i_04_xmm:
   dw  16384,  21407,  16384,   8867 ; movq-> w05 w04 w01 w00
   dw  16384,   8867, -16384, -21407 ; w07 w06 w03 w02
   dw  16384,  -8867,  16384, -21407 ; w13 w12 w09 w08
   dw -16384,  21407,  16384,  -8867 ; w15 w14 w11 w10
   dw  22725,  19266,  19266,  -4520 ; w21 w20 w17 w16
   dw  12873,   4520, -22725, -12873 ; w23 w22 w19 w18
   dw  12873, -22725,   4520, -12873 ; w29 w28 w25 w24
   dw   4520,  19266,  19266, -22725 ; w31 w30 w27 w26
 
 ; %3 for rows 1,7 - constants are multiplied by cos_1_16
 tab_i_17_xmm:
   dw  22725,  29692,  22725,  12299 ; movq-> w05 w04 w01 w00
   dw  22725,  12299, -22725, -29692 ; w07 w06 w03 w02
   dw  22725, -12299,  22725, -29692 ; w13 w12 w09 w08
   dw -22725,  29692,  22725, -12299 ; w15 w14 w11 w10
   dw  31521,  26722,  26722,  -6270 ; w21 w20 w17 w16
   dw  17855,   6270, -31521, -17855 ; w23 w22 w19 w18
   dw  17855, -31521,   6270, -17855 ; w29 w28 w25 w24
   dw   6270,  26722,  26722, -31521 ; w31 w30 w27 w26
 
 ; %3 for rows 2,6 - constants are multiplied by cos_2_16
 tab_i_26_xmm:
   dw  21407,  27969,  21407,  11585 ; movq-> w05 w04 w01 w00
   dw  21407,  11585, -21407, -27969 ; w07 w06 w03 w02
   dw  21407, -11585,  21407, -27969 ; w13 w12 w09 w08
   dw -21407,  27969,  21407, -11585 ; w15 w14 w11 w10
   dw  29692,  25172,  25172,  -5906 ; w21 w20 w17 w16
   dw  16819,   5906, -29692, -16819 ; w23 w22 w19 w18
   dw  16819, -29692,   5906, -16819 ; w29 w28 w25 w24
   dw   5906,  25172,  25172, -29692 ; w31 w30 w27 w26
 
 ; %3 for rows 3,5 - constants are multiplied by cos_3_16
 tab_i_35_xmm:
   dw  19266,  25172,  19266,  10426 ; movq-> w05 w04 w01 w00
   dw  19266,  10426, -19266, -25172 ; w07 w06 w03 w02
   dw  19266, -10426,  19266, -25172 ; w13 w12 w09 w08
   dw -19266,  25172,  19266, -10426 ; w15 w14 w11 w10
   dw  26722,  22654,  22654,  -5315 ; w21 w20 w17 w16
   dw  15137,   5315, -26722, -15137 ; w23 w22 w19 w18
   dw  15137, -26722,   5315, -15137 ; w29 w28 w25 w24
   dw   5315,  22654,  22654, -26722 ; w31 w30 w27 w26
 
 ;=============================================================================
 ; Code
 ;=============================================================================
 
 SECTION .text
 
 cglobal idct_3dne
 
 ;-----------------------------------------------------------------------------
 ; void idct_3dne(uint16_t block[64]);
 ;-----------------------------------------------------------------------------
 
 ALIGN 16
 idct_3dne:
   mov eax, [esp+4]
 
 ;   DCT_8_INV_ROW_1_s [eax+64], [eax+64], tab_i_04_sse, rounder_4 ;rounder_4=0
   pshufw mm0, [eax+64],10001000b        ; x2 x0 x2 x0
   movq mm3, [tab_i_04_xmm]          ; 3     ; w05 w04 w01 w00
   pshufw mm1, [eax+64+8],10001000b  ; x6 x4 x6 x4
   movq mm4, [tab_i_04_xmm+8]        ; 4     ; w07 w06 w03 w02
   pshufw mm2, [eax+64],11011101b        ; x3 x1 x3 x1
   pshufw mm5, [eax+64+8],11011101b  ; x7 x5 x7 x5
   movq mm6, [tab_i_04_xmm+32]   ; 6     ; w21 w20 w17 w16
   pmaddwd mm3, mm0              ; x2*w05+x0*w04 x2*w01+x0*w00
   movq mm7, [tab_i_04_xmm+40]   ; 7     ; w23 w22 w19 w18 ;
   pmaddwd mm0, [tab_i_04_xmm+16]; x2*w13+x0*w12 x2*w09+x0*w08
   pmaddwd mm4, mm1              ; x6*w07+x4*w06 x6*w03+x4*w02