defbf561.h

uboot1.3.0 for s3c2440, 支持nand flash启动

#define DMA2_7_NEXT_DESC_PTR	0xFFC00DC0	/* DMA2 Channel 7 Next Descripter Ptr Reg */
#define DMA2_7_START_ADDR	0xFFC00DC4	/* DMA2 Channel 7 Start Address */
#define DMA2_7_X_COUNT		0xFFC00DD0	/* DMA2 Channel 7 Inner Loop Count */
#define DMA2_7_Y_COUNT		0xFFC00DD8	/* DMA2 Channel 7 Outer Loop Count */
#define DMA2_7_X_MODIFY		0xFFC00DD4	/* DMA2 Channel 7 Inner Loop Addr Increment */
#define DMA2_7_Y_MODIFY		0xFFC00DDC	/* DMA2 Channel 7 Outer Loop Addr Increment */
#define DMA2_7_CURR_DESC_PTR	0xFFC00DE0	/* DMA2 Channel 7 Current Descriptor Pointer */
#define DMA2_7_CURR_ADDR	0xFFC00DE4	/* DMA2 Channel 7 Current Address Pointer */
#define DMA2_7_CURR_X_COUNT	0xFFC00DF0	/* DMA2 Channel 7 Current Inner Loop Count */
#define DMA2_7_CURR_Y_COUNT	0xFFC00DF8	/* DMA2 Channel 7 Current Outer Loop Count */
#define DMA2_7_IRQ_STATUS	0xFFC00DE8	/* DMA2 Channel 7 Interrupt Status Register */
#define DMA2_7_PERIPHERAL_MAP	0xFFC00DEC	/* DMA2 Channel 7 Peripheral Map Register */

#define DMA2_8_CONFIG		0xFFC00E08	/* DMA2 Channel 8 Configuration register */
#define DMA2_8_NEXT_DESC_PTR	0xFFC00E00	/* DMA2 Channel 8 Next Descripter Ptr Reg */
#define DMA2_8_START_ADDR	0xFFC00E04	/* DMA2 Channel 8 Start Address */
#define DMA2_8_X_COUNT		0xFFC00E10	/* DMA2 Channel 8 Inner Loop Count */
#define DMA2_8_Y_COUNT		0xFFC00E18	/* DMA2 Channel 8 Outer Loop Count */
#define DMA2_8_X_MODIFY		0xFFC00E14	/* DMA2 Channel 8 Inner Loop Addr Increment */
#define DMA2_8_Y_MODIFY		0xFFC00E1C	/* DMA2 Channel 8 Outer Loop Addr Increment */
#define DMA2_8_CURR_DESC_PTR	0xFFC00E20	/* DMA2 Channel 8 Current Descriptor Pointer */
#define DMA2_8_CURR_ADDR	0xFFC00E24	/* DMA2 Channel 8 Current Address Pointer */
#define DMA2_8_CURR_X_COUNT	0xFFC00E30	/* DMA2 Channel 8 Current Inner Loop Count */
#define DMA2_8_CURR_Y_COUNT	0xFFC00E38	/* DMA2 Channel 8 Current Outer Loop Count */
#define DMA2_8_IRQ_STATUS	0xFFC00E28	/* DMA2 Channel 8 Interrupt Status Register */
#define DMA2_8_PERIPHERAL_MAP	0xFFC00E2C	/* DMA2 Channel 8 Peripheral Map Register */

#define DMA2_9_CONFIG		0xFFC00E48	/* DMA2 Channel 9 Configuration register */
#define DMA2_9_NEXT_DESC_PTR	0xFFC00E40	/* DMA2 Channel 9 Next Descripter Ptr Reg */
#define DMA2_9_START_ADDR	0xFFC00E44	/* DMA2 Channel 9 Start Address */
#define DMA2_9_X_COUNT		0xFFC00E50	/* DMA2 Channel 9 Inner Loop Count */
#define DMA2_9_Y_COUNT		0xFFC00E58	/* DMA2 Channel 9 Outer Loop Count */
#define DMA2_9_X_MODIFY		0xFFC00E54	/* DMA2 Channel 9 Inner Loop Addr Increment */
#define DMA2_9_Y_MODIFY		0xFFC00E5C	/* DMA2 Channel 9 Outer Loop Addr Increment */
#define DMA2_9_CURR_DESC_PTR	0xFFC00E60	/* DMA2 Channel 9 Current Descriptor Pointer */
#define DMA2_9_CURR_ADDR	0xFFC00E64	/* DMA2 Channel 9 Current Address Pointer */
#define DMA2_9_CURR_X_COUNT	0xFFC00E70	/* DMA2 Channel 9 Current Inner Loop Count */
#define DMA2_9_CURR_Y_COUNT	0xFFC00E78	/* DMA2 Channel 9 Current Outer Loop Count */
#define DMA2_9_IRQ_STATUS	0xFFC00E68	/* DMA2 Channel 9 Interrupt Status Register */
#define DMA2_9_PERIPHERAL_MAP	0xFFC00E6C	/* DMA2 Channel 9 Peripheral Map Register */

#define DMA2_10_CONFIG		0xFFC00E88	/* DMA2 Channel 10 Configuration register */
#define DMA2_10_NEXT_DESC_PTR	0xFFC00E80	/* DMA2 Channel 10 Next Descripter Ptr Reg */
#define DMA2_10_START_ADDR	0xFFC00E84	/* DMA2 Channel 10 Start Address */
#define DMA2_10_X_COUNT		0xFFC00E90	/* DMA2 Channel 10 Inner Loop Count */
#define DMA2_10_Y_COUNT		0xFFC00E98	/* DMA2 Channel 10 Outer Loop Count */
#define DMA2_10_X_MODIFY	0xFFC00E94	/* DMA2 Channel 10 Inner Loop Addr Increment */
#define DMA2_10_Y_MODIFY	0xFFC00E9C	/* DMA2 Channel 10 Outer Loop Addr Increment */
#define DMA2_10_CURR_DESC_PTR	0xFFC00EA0	/* DMA2 Channel 10 Current Descriptor Pointer */
#define DMA2_10_CURR_ADDR	0xFFC00EA4	/* DMA2 Channel 10 Current Address Pointer */
#define DMA2_10_CURR_X_COUNT	0xFFC00EB0	/* DMA2 Channel 10 Current Inner Loop Count */
#define DMA2_10_CURR_Y_COUNT	0xFFC00EB8	/* DMA2 Channel 10 Current Outer Loop Count */
#define DMA2_10_IRQ_STATUS	0xFFC00EA8	/* DMA2 Channel 10 Interrupt Status Register */
#define DMA2_10_PERIPHERAL_MAP	0xFFC00EAC	/* DMA2 Channel 10 Peripheral Map Register */

#define DMA2_11_CONFIG		0xFFC00EC8	/* DMA2 Channel 11 Configuration register */
#define DMA2_11_NEXT_DESC_PTR	0xFFC00EC0	/* DMA2 Channel 11 Next Descripter Ptr Reg */
#define DMA2_11_START_ADDR	0xFFC00EC4	/* DMA2 Channel 11 Start Address */
#define DMA2_11_X_COUNT		0xFFC00ED0	/* DMA2 Channel 11 Inner Loop Count */
#define DMA2_11_Y_COUNT		0xFFC00ED8	/* DMA2 Channel 11 Outer Loop Count */
#define DMA2_11_X_MODIFY	0xFFC00ED4	/* DMA2 Channel 11 Inner Loop Addr Increment */
#define DMA2_11_Y_MODIFY	0xFFC00EDC	/* DMA2 Channel 11 Outer Loop Addr Increment */
#define DMA2_11_CURR_DESC_PTR	0xFFC00EE0	/* DMA2 Channel 11 Current Descriptor Pointer */
#define DMA2_11_CURR_ADDR	0xFFC00EE4	/* DMA2 Channel 11 Current Address Pointer */
#define DMA2_11_CURR_X_COUNT	0xFFC00EF0	/* DMA2 Channel 11 Current Inner Loop Count */
#define DMA2_11_CURR_Y_COUNT	0xFFC00EF8	/* DMA2 Channel 11 Current Outer Loop Count */
#define DMA2_11_IRQ_STATUS	0xFFC00EE8	/* DMA2 Channel 11 Interrupt Status Register */
#define DMA2_11_PERIPHERAL_MAP	0xFFC00EEC	/* DMA2 Channel 11 Peripheral Map Register */

/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
#define MDMA2_D0_CONFIG		0xFFC00F08	/* MemDMA2 Stream 0 Destination Configuration register */
#define MDMA2_D0_NEXT_DESC_PTR	0xFFC00F00	/* MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
#define MDMA2_D0_START_ADDR	0xFFC00F04	/* MemDMA2 Stream 0 Destination Start Address */
#define MDMA2_D0_X_COUNT	0xFFC00F10	/* MemDMA2 Stream 0 Dest Inner-Loop Count register */
#define MDMA2_D0_Y_COUNT	0xFFC00F18	/* MemDMA2 Stream 0 Dest Outer-Loop Count register */
#define MDMA2_D0_X_MODIFY	0xFFC00F14	/* MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
#define MDMA2_D0_Y_MODIFY	0xFFC00F1C	/* MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
#define MDMA2_D0_CURR_DESC_PTR	0xFFC00F20	/* MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
#define MDMA2_D0_CURR_ADDR	0xFFC00F24	/* MemDMA2 Stream 0 Destination Current Address */
#define MDMA2_D0_CURR_X_COUNT	0xFFC00F30	/* MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
#define MDMA2_D0_CURR_Y_COUNT	0xFFC00F38	/* MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
#define MDMA2_D0_IRQ_STATUS	0xFFC00F28	/* MemDMA2 Stream 0 Dest Interrupt/Status Register */
#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C	/* MemDMA2 Stream 0 Destination Peripheral Map register */

#define MDMA2_S0_CONFIG		0xFFC00F48	/* MemDMA2 Stream 0 Source Configuration register */
#define MDMA2_S0_NEXT_DESC_PTR	0xFFC00F40	/* MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
#define MDMA2_S0_START_ADDR	0xFFC00F44	/* MemDMA2 Stream 0 Source Start Address */
#define MDMA2_S0_X_COUNT	0xFFC00F50	/* MemDMA2 Stream 0 Source Inner-Loop Count register */
#define MDMA2_S0_Y_COUNT	0xFFC00F58	/* MemDMA2 Stream 0 Source Outer-Loop Count register */
#define MDMA2_S0_X_MODIFY	0xFFC00F54	/* MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
#define MDMA2_S0_Y_MODIFY	0xFFC00F5C	/* MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
#define MDMA2_S0_CURR_DESC_PTR	0xFFC00F60	/* MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
#define MDMA2_S0_CURR_ADDR	0xFFC00F64	/* MemDMA2 Stream 0 Source Current Address */
#define MDMA2_S0_CURR_X_COUNT	0xFFC00F70	/* MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
#define MDMA2_S0_CURR_Y_COUNT	0xFFC00F78	/* MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
#define MDMA2_S0_IRQ_STATUS	0xFFC00F68	/* MemDMA2 Stream 0 Source Interrupt/Status Register */
#define MDMA2_S0_PERIPHERAL_MAP	0xFFC00F6C	/* MemDMA2 Stream 0 Source Peripheral Map register */

#define MDMA2_D1_CONFIG		0xFFC00F88	/* MemDMA2 Stream 1 Destination Configuration register */
#define MDMA2_D1_NEXT_DESC_PTR	0xFFC00F80	/* MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
#define MDMA2_D1_START_ADDR	0xFFC00F84	/* MemDMA2 Stream 1 Destination Start Address */
#define MDMA2_D1_X_COUNT	0xFFC00F90	/* MemDMA2 Stream 1 Dest Inner-Loop Count register */
#define MDMA2_D1_Y_COUNT	0xFFC00F98	/* MemDMA2 Stream 1 Dest Outer-Loop Count register */
#define MDMA2_D1_X_MODIFY	0xFFC00F94	/* MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
#define MDMA2_D1_Y_MODIFY	0xFFC00F9C	/* MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
#define MDMA2_D1_CURR_DESC_PTR	0xFFC00FA0	/* MemDMA2 Stream 1 Destination Current Descriptor Ptr */
#define MDMA2_D1_CURR_ADDR	0xFFC00FA4	/* MemDMA2 Stream 1 Destination Current Address reg */
#define MDMA2_D1_CURR_X_COUNT	0xFFC00FB0	/* MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
#define MDMA2_D1_CURR_Y_COUNT	0xFFC00FB8	/* MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
#define MDMA2_D1_IRQ_STATUS	0xFFC00FA8	/* MemDMA2 Stream 1 Destination Interrupt/Status Reg */
#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC	/* MemDMA2 Stream 1 Destination Peripheral Map register */

#define MDMA2_S1_CONFIG		0xFFC00FC8	/* MemDMA2 Stream 1 Source Configuration register */
#define MDMA2_S1_NEXT_DESC_PTR	0xFFC00FC0	/* MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
#define MDMA2_S1_START_ADDR	0xFFC00FC4	/* MemDMA2 Stream 1 Source Start Address */
#define MDMA2_S1_X_COUNT	0xFFC00FD0	/* MemDMA2 Stream 1 Source Inner-Loop Count register */
#define MDMA2_S1_Y_COUNT	0xFFC00FD8	/* MemDMA2 Stream 1 Source Outer-Loop Count register */
#define MDMA2_S1_X_MODIFY	0xFFC00FD4	/* MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
#define MDMA2_S1_Y_MODIFY	0xFFC00FDC	/* MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
#define MDMA2_S1_CURR_DESC_PTR	0xFFC00FE0	/* MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
#define MDMA2_S1_CURR_ADDR	0xFFC00FE4	/* MemDMA2 Stream 1 Source Current Address */
#define MDMA2_S1_CURR_X_COUNT	0xFFC00FF0	/* MemDMA2 Stream 1 Source Current Inner-Loop Count */
#define MDMA2_S1_CURR_Y_COUNT	0xFFC00FF8	/* MemDMA2 Stream 1 Source Current Outer-Loop Count */
#define MDMA2_S1_IRQ_STATUS	0xFFC00FE8	/* MemDMA2 Stream 1 Source Interrupt/Status Register */
#define MDMA2_S1_PERIPHERAL_MAP	0xFFC00FEC	/* MemDMA2 Stream 1 Source Peripheral Map register */

/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
#define IMDMA_D0_CONFIG		0xFFC01808	/* IMDMA Stream 0 Destination Configuration */
#define IMDMA_D0_NEXT_DESC_PTR	0xFFC01800	/* IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
#define IMDMA_D0_START_ADDR	0xFFC01804	/* IMDMA Stream 0 Destination Start Address */
#define IMDMA_D0_X_COUNT	0xFFC01810	/* IMDMA Stream 0 Destination Inner-Loop Count */
#define IMDMA_D0_Y_COUNT	0xFFC01818	/* IMDMA Stream 0 Destination Outer-Loop Count */
#define IMDMA_D0_X_MODIFY	0xFFC01814	/* IMDMA Stream 0 Dest Inner-Loop Address-Increment */
#define IMDMA_D0_Y_MODIFY	0xFFC0181C	/* IMDMA Stream 0 Dest Outer-Loop Address-Increment */
#define IMDMA_D0_CURR_DESC_PTR	0xFFC01820	/* IMDMA Stream 0 Destination Current Descriptor Ptr */
#define IMDMA_D0_CURR_ADDR	0xFFC01824	/* IMDMA Stream 0 Destination Current Address */
#define IMDMA_D0_CURR_X_COUNT	0xFFC01830	/* IMDMA Stream 0 Destination Current Inner-Loop Count */
#define IMDMA_D0_CURR_Y_COUNT	0xFFC01838	/* IMDMA Stream 0 Destination Current Outer-Loop Count */
#define IMDMA_D0_IRQ_STATUS	0xFFC01828	/* IMDMA Stream 0 Destination Interrupt/Status */

#define IMDMA_S0_CONFIG		0xFFC01848	/* IMDMA Stream 0 Source Configuration */
#define IMDMA_S0_NEXT_DESC_PTR	0xFFC01840	/* IMDMA Stream 0 Source Next Descriptor Ptr Reg */
#define IMDMA_S0_START_ADDR	0xFFC01844	/* IMDMA Stream 0 Source Start Address */
#define IMDMA_S0_X_COUNT	0xFFC01850	/* IMDMA Stream 0 Source Inner-Loop Count */
#define IMDMA_S0_Y_COUNT	0xFFC01858	/* IMDMA Stream 0 Source Outer-Loop Count */
#define IMDMA_S0_X_MODIFY	0xFFC01854	/* IMDMA Stream 0 Source Inner-Loop Address-Increment */
#define IMDMA_S0_Y_MODIFY	0xFFC0185C	/* IMDMA Stream 0 Source Outer-Loop Address-Increment */
#define IMDMA_S0_CURR_DESC_PTR	0xFFC01860	/* IMDMA Stream 0 Source Current Descriptor Ptr reg */
#define IMDMA_S0_CURR_ADDR	0xFFC01864	/* IMDMA Stream 0 Source Current Address */
#define IMDMA_S0_CURR_X_COUNT	0xFFC01870	/* IMDMA Stream 0 Source Current Inner-Loop Count */
#define IMDMA_S0_CURR_Y_COUNT	0xFFC01878	/* IMDMA Stream 0 Source Current Outer-Loop Count */
#define IMDMA_S0_IRQ_STATUS	0xFFC01868	/* IMDMA Stream 0 Source Interrupt/Status */

#define IMDMA_D1_CONFIG		0xFFC01888	/* IMDMA Stream 1 Destination Configuration */
#define IMDMA_D1_NEXT_DESC_PTR	0xFFC01880	/* IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
#define IMDMA_D1_START_ADDR	0xFFC01884	/* IMDMA Stream 1 Destination Start Address */
#define IMDMA_D1_X_COUNT	0xFFC01890	/* IMDMA Stream 1 Destination Inner-Loop Count */
#define IMDMA_D1_Y_COUNT	0xFFC01898	/* IMDMA Stream 1 Destination Outer-Loop Count */
#define IMDMA_D1_X_MODIFY	0xFFC01894	/* IMDMA Stream 1 Dest Inner-Loop Address-Increment */
#define IMDMA_D1_Y_MODIFY	0xFFC0189C	/* IMDMA Stream 1 Dest Outer-Loop Address-Increment */
#define IMDMA_D1_CURR_DESC_PTR	0xFFC018A0	/* IMDMA Stream 1 Destination Current Descriptor Ptr */
#define IMDMA_D1_CURR_ADDR	0xFFC018A4	/* IMDMA Stream 1 Destination Current Address */
#define IMDMA_D1_CURR_X_COUNT	0xFFC018B0	/* IMDMA Stream 1 Destination Current Inner-Loop Count */
#define IMDMA_D1_CURR_Y_COUNT	0xFFC018B8	/* IMDMA Stream 1 Destination Current Outer-Loop Count */
#define IMDMA_D1_IRQ_STATUS	0xFFC018A8	/* IMDMA Stream 1 Destination Interrupt/Status */

#define IMDMA_S1_CONFIG		0xFFC018C8	/* IMDMA Stream 1 Source Configuration */
#define IMDMA_S1_NEXT_DESC_PTR	0xFFC018C0	/* IMDMA Stream 1 Source Next Descriptor Ptr Reg */
#define IMDMA_S1_START_ADDR	0xFFC018C4	/* IMDMA Stream 1 Source Start Address */
#define IMDMA_S1_X_COUNT	0xFFC018D0	/* IMDMA Stream 1 Source Inner-Loop Count */
#define IMDMA_S1_Y_COUNT	0xFFC018D8	/* IMDMA Stream 1 Source Outer-Loop Count */
#define IMDMA_S1_X_MODIFY	0xFFC018D4	/* IMDMA Stream 1 Source Inner-Loop Address-Increment */
#define IMDMA_S1_Y_MODIFY	0xFFC018DC	/* IMDMA Stream 1 Source Outer-Loop Address-Increment */
#define IMDMA_S1_CURR_DESC_PTR	0xFFC018E0	/* IMDMA Stream 1 Source Current Descriptor Ptr reg */
#define IMDMA_S1_CURR_ADDR	0xFFC018E4	/* IMDMA Stream 1 Source Current Address */
#define IMDMA_S1_CURR_X_COUNT	0xFFC018F0	/* IMDMA Stream 1 Source Current Inner-Loop Count */
#define IMDMA_S1_CURR_Y_COUNT	0xFFC018F8	/* IMDMA Stream 1 Source Current Outer-Loop Count */
#define IMDMA_S1_IRQ_STATUS	0xFFC018E8	/* IMDMA Stream 1 Source Interrupt/Status */

/*
 * System MMR Register Bits
 */

/* PLL AND RESET MASKS */

/* PLL_CTL Masks */
#define PLL_CLKIN		0x00000000	/* Pass CLKIN to PLL */
#define PLL_CLKIN_DIV2		0x00000001	/* Pass CLKIN/2 to PLL */
#define PLL_OFF			0x00000002	/* Shut off PLL clocks */
#define STOPCK_OFF		0x00000008	/* Core clock off */
#define PDWN			0x00000020	/* Put the PLL in a Deep Sleep state */
#define BYPASS			0x00000100	/* Bypass the PLL */

/* PLL_DIV Masks */

#define SCLK_DIV(x)		(x)		/* SCLK = VCO / x */

#define CCLK_DIV1		0x00000000	/* CCLK = VCO / 1 */
#define CCLK_DIV2		0x00000010	/* CCLK = VCO / 2 */
#define CCLK_DIV4		0x00000020	/* CCLK = VCO / 4 */
#define CCLK_DIV8		0x00000030	/* CCLK = VCO / 8 */

/* SWRST Mask */
#define SYSTEM_RESET		0x00000007	/* Initiates a system software reset */
#define SWRST_DBL_FAULT_B	0x00000800	/* SWRST Core B Double Fault */
#define SWRST_DBL_FAULT_A	0x00001000	/* SWRST Core A Double Fault */
#define SWRST_WDT_B		0x00002000	/* SWRST Watchdog B */
#define SWRST_WDT_A		0x00004000	/* SWRST Watchdog A */
#define SWRST_OCCURRED		0x00008000	/* SWRST Status */

/*
 * SYSTEM INTERRUPT CONTROLLER MASKS
 * SICu_IARv Masks
 * u = A or B