defbf561.h

uboot1.3.0 for s3c2440, 支持nand flash启动

#define FIO1_EDGE		0xFFC01538	/* Flag  Interrupt Sensitivity register */
#define FIO1_BOTH		0xFFC0153C	/* Flag Set on Both Edges register */
#define FIO1_INEN		0xFFC01540	/* Flag Input Enable register */

/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
#define FIO2_FLAG_D		0xFFC01700	/* Flag Data register */
#define FIO2_FLAG_C		0xFFC01704	/* Flag Clear register */
#define FIO2_FLAG_S		0xFFC01708	/* Flag Set register */
#define FIO2_FLAG_T		0xFFC0170C	/* Flag Toggle register */
#define FIO2_MASKA_D		0xFFC01710	/* Flag Mask Interrupt A Data register */
#define FIO2_MASKA_C		0xFFC01714	/* Flag Mask Interrupt A Clear register */
#define FIO2_MASKA_S		0xFFC01718	/* Flag Mask Interrupt A Set register */
#define FIO2_MASKA_T		0xFFC0171C	/* Flag Mask Interrupt A Toggle register */
#define FIO2_MASKB_D		0xFFC01720	/* Flag Mask Interrupt B Data register */
#define FIO2_MASKB_C		0xFFC01724	/* Flag Mask Interrupt B Clear register */
#define FIO2_MASKB_S		0xFFC01728	/* Flag Mask Interrupt B Set register */
#define FIO2_MASKB_T		0xFFC0172C	/* Flag Mask Interrupt B Toggle register */
#define FIO2_DIR		0xFFC01730	/* Flag Direction register */
#define FIO2_POLAR		0xFFC01734	/* Flag Polarity register */
#define FIO2_EDGE		0xFFC01738	/* Flag Interrupt Sensitivity register */
#define FIO2_BOTH		0xFFC0173C	/* Flag Set on Both Edges register */
#define FIO2_INEN		0xFFC01740	/* Flag Input Enable register */

/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
#define SPORT0_TCR1		0xFFC00800	/* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_TCR2		0xFFC00804	/* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_TCLKDIV		0xFFC00808	/* SPORT0 Transmit Clock Divider */
#define SPORT0_TFSDIV		0xFFC0080C	/* SPORT0 Transmit Frame Sync Divider */
#define SPORT0_TX		0xFFC00810	/* SPORT0 TX Data Register */
#define SPORT0_RX		0xFFC00818	/* SPORT0 RX Data Register */
#define SPORT0_RCR1		0xFFC00820	/* SPORT0 Transmit Configuration 1 Register */
#define SPORT0_RCR2		0xFFC00824	/* SPORT0 Transmit Configuration 2 Register */
#define SPORT0_RCLKDIV		0xFFC00828	/* SPORT0 Receive Clock Divider */
#define SPORT0_RFSDIV		0xFFC0082C	/* SPORT0 Receive Frame Sync Divider */
#define SPORT0_STAT		0xFFC00830	/* SPORT0 Status Register */
#define SPORT0_CHNL		0xFFC00834	/* SPORT0 Current Channel Register */
#define SPORT0_MCMC1		0xFFC00838	/* SPORT0 Multi-Channel Configuration Register 1 */
#define SPORT0_MCMC2		0xFFC0083C	/* SPORT0 Multi-Channel Configuration Register 2 */
#define SPORT0_MTCS0		0xFFC00840	/* SPORT0 Multi-Channel Transmit Select Register 0 */
#define SPORT0_MTCS1		0xFFC00844	/* SPORT0 Multi-Channel Transmit Select Register 1 */
#define SPORT0_MTCS2		0xFFC00848	/* SPORT0 Multi-Channel Transmit Select Register 2 */
#define SPORT0_MTCS3		0xFFC0084C	/* SPORT0 Multi-Channel Transmit Select Register 3 */
#define SPORT0_MRCS0		0xFFC00850	/* SPORT0 Multi-Channel Receive Select Register 0 */
#define SPORT0_MRCS1		0xFFC00854	/* SPORT0 Multi-Channel Receive Select Register 1 */
#define SPORT0_MRCS2		0xFFC00858	/* SPORT0 Multi-Channel Receive Select Register 2 */
#define SPORT0_MRCS3		0xFFC0085C	/* SPORT0 Multi-Channel Receive Select Register 3 */

/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
#define SPORT1_TCR1		0xFFC00900	/* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_TCR2		0xFFC00904	/* SPORT1 Transmit Configuration 2 Register */
#define SPORT1_TCLKDIV		0xFFC00908	/* SPORT1 Transmit Clock Divider */
#define SPORT1_TFSDIV		0xFFC0090C	/* SPORT1 Transmit Frame Sync Divider */
#define SPORT1_TX		0xFFC00910	/* SPORT1 TX Data Register */
#define SPORT1_RX		0xFFC00918	/* SPORT1 RX Data Register */
#define SPORT1_RCR1		0xFFC00920	/* SPORT1 Transmit Configuration 1 Register */
#define SPORT1_RCR2		0xFFC00924	/* SPORT1 Transmit Configuration 2 Register */
#define SPORT1_RCLKDIV		0xFFC00928	/* SPORT1 Receive Clock Divider */
#define SPORT1_RFSDIV		0xFFC0092C	/* SPORT1 Receive Frame Sync Divider */
#define SPORT1_STAT		0xFFC00930	/* SPORT1 Status Register */
#define SPORT1_CHNL		0xFFC00934	/* SPORT1 Current Channel Register */
#define SPORT1_MCMC1		0xFFC00938	/* SPORT1 Multi-Channel Configuration Register 1 */
#define SPORT1_MCMC2		0xFFC0093C	/* SPORT1 Multi-Channel Configuration Register 2 */
#define SPORT1_MTCS0		0xFFC00940	/* SPORT1 Multi-Channel Transmit Select Register 0 */
#define SPORT1_MTCS1		0xFFC00944	/* SPORT1 Multi-Channel Transmit Select Register 1 */
#define SPORT1_MTCS2		0xFFC00948	/* SPORT1 Multi-Channel Transmit Select Register 2 */
#define SPORT1_MTCS3		0xFFC0094C	/* SPORT1 Multi-Channel Transmit Select Register 3 */
#define SPORT1_MRCS0		0xFFC00950	/* SPORT1 Multi-Channel Receive Select Register 0 */
#define SPORT1_MRCS1		0xFFC00954	/* SPORT1 Multi-Channel Receive Select Register 1 */
#define SPORT1_MRCS2		0xFFC00958	/* SPORT1 Multi-Channel Receive Select Register 2 */
#define SPORT1_MRCS3		0xFFC0095C	/* SPORT1 Multi-Channel Receive Select Register 3 */

/* Asynchronous Memory Controller - External Bus Interface Unit */
#define EBIU_AMGCTL		0xFFC00A00	/* Asynchronous Memory Global Control Register */
#define EBIU_AMBCTL0		0xFFC00A04	/* Asynchronous Memory Bank Control Register 0 */
#define EBIU_AMBCTL1		0xFFC00A08	/* Asynchronous Memory Bank Control Register 1 */

/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
#define EBIU_SDGCTL		0xFFC00A10	/* SDRAM Global Control Register */
#define EBIU_SDBCTL		0xFFC00A14	/* SDRAM Bank Control Register */
#define EBIU_SDRRC		0xFFC00A18	/* SDRAM Refresh Rate Control Register */
#define EBIU_SDSTAT		0xFFC00A1C	/* SDRAM Status Register */

/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
#define PPI0_CONTROL		0xFFC01000	/* PPI0 Control register */
#define PPI0_STATUS		0xFFC01004	/* PPI0 Status register */
#define PPI0_COUNT		0xFFC01008	/* PPI0 Transfer Count register */
#define PPI0_DELAY		0xFFC0100C	/* PPI0 Delay Count register */
#define PPI0_FRAME		0xFFC01010	/* PPI0 Frame Length register */

/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
#define PPI1_CONTROL		0xFFC01300	/* PPI1 Control register */
#define PPI1_STATUS		0xFFC01304	/* PPI1 Status register */
#define PPI1_COUNT		0xFFC01308	/* PPI1 Transfer Count register */
#define PPI1_DELAY		0xFFC0130C	/* PPI1 Delay Count register */
#define PPI1_FRAME		0xFFC01310	/* PPI1 Frame Length register */

/* DMA Traffic controls */
#define DMA_TCPER		0xFFC00B0C	/* Traffic Control Periods Register */
#define DMA_TCCNT		0xFFC00B10	/* Traffic Control Current Counts Register */
#define DMA_TC_PER		0xFFC00B0C	/* Traffic Control Periods Register */
#define DMA_TC_CNT		0xFFC00B10	/* Traffic Control Current Counts Register */

/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
#define DMA1_0_CONFIG		0xFFC01C08	/* DMA1 Channel 0 Configuration register */
#define DMA1_0_NEXT_DESC_PTR	0xFFC01C00	/* DMA1 Channel 0 Next Descripter Ptr Reg */
#define DMA1_0_START_ADDR	0xFFC01C04	/* DMA1 Channel 0 Start Address */
#define DMA1_0_X_COUNT		0xFFC01C10	/* DMA1 Channel 0 Inner Loop Count */
#define DMA1_0_Y_COUNT		0xFFC01C18	/* DMA1 Channel 0 Outer Loop Count */
#define DMA1_0_X_MODIFY		0xFFC01C14	/* DMA1 Channel 0 Inner Loop Addr Increment */
#define DMA1_0_Y_MODIFY		0xFFC01C1C	/* DMA1 Channel 0 Outer Loop Addr Increment */
#define DMA1_0_CURR_DESC_PTR	0xFFC01C20	/* DMA1 Channel 0 Current Descriptor Pointer */
#define DMA1_0_CURR_ADDR	0xFFC01C24	/* DMA1 Channel 0 Current Address Pointer */
#define DMA1_0_CURR_X_COUNT	0xFFC01C30	/* DMA1 Channel 0 Current Inner Loop Count */
#define DMA1_0_CURR_Y_COUNT	0xFFC01C38	/* DMA1 Channel 0 Current Outer Loop Count */
#define DMA1_0_IRQ_STATUS	0xFFC01C28	/* DMA1 Channel 0 Interrupt Status Register */
#define DMA1_0_PERIPHERAL_MAP	0xFFC01C2C	/* DMA1 Channel 0 Peripheral Map Register */

#define DMA1_1_CONFIG		0xFFC01C48	/* DMA1 Channel 1 Configuration register */
#define DMA1_1_NEXT_DESC_PTR	0xFFC01C40	/* DMA1 Channel 1 Next Descripter Ptr Reg */
#define DMA1_1_START_ADDR	0xFFC01C44	/* DMA1 Channel 1 Start Address */
#define DMA1_1_X_COUNT		0xFFC01C50	/* DMA1 Channel 1 Inner Loop Count */
#define DMA1_1_Y_COUNT		0xFFC01C58	/* DMA1 Channel 1 Outer Loop Count */
#define DMA1_1_X_MODIFY		0xFFC01C54	/* DMA1 Channel 1 Inner Loop Addr Increment */
#define DMA1_1_Y_MODIFY		0xFFC01C5C	/* DMA1 Channel 1 Outer Loop Addr Increment */
#define DMA1_1_CURR_DESC_PTR	0xFFC01C60	/* DMA1 Channel 1 Current Descriptor Pointer */
#define DMA1_1_CURR_ADDR	0xFFC01C64	/* DMA1 Channel 1 Current Address Pointer */
#define DMA1_1_CURR_X_COUNT	0xFFC01C70	/* DMA1 Channel 1 Current Inner Loop Count */
#define DMA1_1_CURR_Y_COUNT	0xFFC01C78	/* DMA1 Channel 1 Current Outer Loop Count */
#define DMA1_1_IRQ_STATUS	0xFFC01C68	/* DMA1 Channel 1 Interrupt Status Register */
#define DMA1_1_PERIPHERAL_MAP	0xFFC01C6C	/* DMA1 Channel 1 Peripheral Map Register */

#define DMA1_2_CONFIG		0xFFC01C88	/* DMA1 Channel 2 Configuration register */
#define DMA1_2_NEXT_DESC_PTR	0xFFC01C80	/* DMA1 Channel 2 Next Descripter Ptr Reg */
#define DMA1_2_START_ADDR	0xFFC01C84	/* DMA1 Channel 2 Start Address */
#define DMA1_2_X_COUNT		0xFFC01C90	/* DMA1 Channel 2 Inner Loop Count */
#define DMA1_2_Y_COUNT		0xFFC01C98	/* DMA1 Channel 2 Outer Loop Count */
#define DMA1_2_X_MODIFY		0xFFC01C94	/* DMA1 Channel 2 Inner Loop Addr Increment */
#define DMA1_2_Y_MODIFY		0xFFC01C9C	/* DMA1 Channel 2 Outer Loop Addr Increment */
#define DMA1_2_CURR_DESC_PTR	0xFFC01CA0	/* DMA1 Channel 2 Current Descriptor Pointer */
#define DMA1_2_CURR_ADDR	0xFFC01CA4	/* DMA1 Channel 2 Current Address Pointer */
#define DMA1_2_CURR_X_COUNT	0xFFC01CB0	/* DMA1 Channel 2 Current Inner Loop Count */
#define DMA1_2_CURR_Y_COUNT	0xFFC01CB8	/* DMA1 Channel 2 Current Outer Loop Count */
#define DMA1_2_IRQ_STATUS	0xFFC01CA8	/* DMA1 Channel 2 Interrupt Status Register */
#define DMA1_2_PERIPHERAL_MAP	0xFFC01CAC	/* DMA1 Channel 2 Peripheral Map Register */

#define DMA1_3_CONFIG		0xFFC01CC8	/* DMA1 Channel 3 Configuration register */
#define DMA1_3_NEXT_DESC_PTR	0xFFC01CC0	/* DMA1 Channel 3 Next Descripter Ptr Reg */
#define DMA1_3_START_ADDR	0xFFC01CC4	/* DMA1 Channel 3 Start Address */
#define DMA1_3_X_COUNT		0xFFC01CD0	/* DMA1 Channel 3 Inner Loop Count */
#define DMA1_3_Y_COUNT		0xFFC01CD8	/* DMA1 Channel 3 Outer Loop Count */
#define DMA1_3_X_MODIFY		0xFFC01CD4	/* DMA1 Channel 3 Inner Loop Addr Increment */
#define DMA1_3_Y_MODIFY		0xFFC01CDC	/* DMA1 Channel 3 Outer Loop Addr Increment */
#define DMA1_3_CURR_DESC_PTR	0xFFC01CE0	/* DMA1 Channel 3 Current Descriptor Pointer */
#define DMA1_3_CURR_ADDR	0xFFC01CE4	/* DMA1 Channel 3 Current Address Pointer */
#define DMA1_3_CURR_X_COUNT	0xFFC01CF0	/* DMA1 Channel 3 Current Inner Loop Count */
#define DMA1_3_CURR_Y_COUNT	0xFFC01CF8	/* DMA1 Channel 3 Current Outer Loop Count */
#define DMA1_3_IRQ_STATUS	0xFFC01CE8	/* DMA1 Channel 3 Interrupt Status Register */
#define DMA1_3_PERIPHERAL_MAP	0xFFC01CEC	/* DMA1 Channel 3 Peripheral Map Register */

#define DMA1_4_CONFIG		0xFFC01D08	/* DMA1 Channel 4 Configuration register */
#define DMA1_4_NEXT_DESC_PTR	0xFFC01D00	/* DMA1 Channel 4 Next Descripter Ptr Reg */
#define DMA1_4_START_ADDR	0xFFC01D04	/* DMA1 Channel 4 Start Address */
#define DMA1_4_X_COUNT		0xFFC01D10	/* DMA1 Channel 4 Inner Loop Count */
#define DMA1_4_Y_COUNT		0xFFC01D18	/* DMA1 Channel 4 Outer Loop Count */
#define DMA1_4_X_MODIFY		0xFFC01D14	/* DMA1 Channel 4 Inner Loop Addr Increment */
#define DMA1_4_Y_MODIFY		0xFFC01D1C	/* DMA1 Channel 4 Outer Loop Addr Increment */
#define DMA1_4_CURR_DESC_PTR	0xFFC01D20	/* DMA1 Channel 4 Current Descriptor Pointer */
#define DMA1_4_CURR_ADDR	0xFFC01D24	/* DMA1 Channel 4 Current Address Pointer */
#define DMA1_4_CURR_X_COUNT	0xFFC01D30	/* DMA1 Channel 4 Current Inner Loop Count */
#define DMA1_4_CURR_Y_COUNT	0xFFC01D38	/* DMA1 Channel 4 Current Outer Loop Count */
#define DMA1_4_IRQ_STATUS	0xFFC01D28	/* DMA1 Channel 4 Interrupt Status Register */
#define DMA1_4_PERIPHERAL_MAP	0xFFC01D2C	/* DMA1 Channel 4 Peripheral Map Register */

#define DMA1_5_CONFIG		0xFFC01D48	/* DMA1 Channel 5 Configuration register */
#define DMA1_5_NEXT_DESC_PTR	0xFFC01D40	/* DMA1 Channel 5 Next Descripter Ptr Reg */
#define DMA1_5_START_ADDR	0xFFC01D44	/* DMA1 Channel 5 Start Address */
#define DMA1_5_X_COUNT		0xFFC01D50	/* DMA1 Channel 5 Inner Loop Count */
#define DMA1_5_Y_COUNT		0xFFC01D58	/* DMA1 Channel 5 Outer Loop Count */
#define DMA1_5_X_MODIFY		0xFFC01D54	/* DMA1 Channel 5 Inner Loop Addr Increment */
#define DMA1_5_Y_MODIFY		0xFFC01D5C	/* DMA1 Channel 5 Outer Loop Addr Increment */
#define DMA1_5_CURR_DESC_PTR	0xFFC01D60	/* DMA1 Channel 5 Current Descriptor Pointer */
#define DMA1_5_CURR_ADDR	0xFFC01D64	/* DMA1 Channel 5 Current Address Pointer */
#define DMA1_5_CURR_X_COUNT	0xFFC01D70	/* DMA1 Channel 5 Current Inner Loop Count */
#define DMA1_5_CURR_Y_COUNT	0xFFC01D78	/* DMA1 Channel 5 Current Outer Loop Count */
#define DMA1_5_IRQ_STATUS	0xFFC01D68	/* DMA1 Channel 5 Interrupt Status Register */
#define DMA1_5_PERIPHERAL_MAP	0xFFC01D6C	/* DMA1 Channel 5 Peripheral Map Register */

#define DMA1_6_CONFIG		0xFFC01D88	/* DMA1 Channel 6 Configuration register */
#define DMA1_6_NEXT_DESC_PTR	0xFFC01D80	/* DMA1 Channel 6 Next Descripter Ptr Reg */
#define DMA1_6_START_ADDR	0xFFC01D84	/* DMA1 Channel 6 Start Address */
#define DMA1_6_X_COUNT		0xFFC01D90	/* DMA1 Channel 6 Inner Loop Count */
#define DMA1_6_Y_COUNT		0xFFC01D98	/* DMA1 Channel 6 Outer Loop Count */
#define DMA1_6_X_MODIFY		0xFFC01D94	/* DMA1 Channel 6 Inner Loop Addr Increment */
#define DMA1_6_Y_MODIFY		0xFFC01D9C	/* DMA1 Channel 6 Outer Loop Addr Increment */
#define DMA1_6_CURR_DESC_PTR	0xFFC01DA0	/* DMA1 Channel 6 Current Descriptor Pointer */
#define DMA1_6_CURR_ADDR	0xFFC01DA4	/* DMA1 Channel 6 Current Address Pointer */
#define DMA1_6_CURR_X_COUNT	0xFFC01DB0	/* DMA1 Channel 6 Current Inner Loop Count */
#define DMA1_6_CURR_Y_COUNT	0xFFC01DB8	/* DMA1 Channel 6 Current Outer Loop Count */
#define DMA1_6_IRQ_STATUS	0xFFC01DA8	/* DMA1 Channel 6 Interrupt Status Register */
#define DMA1_6_PERIPHERAL_MAP	0xFFC01DAC	/* DMA1 Channel 6 Peripheral Map Register */

#define DMA1_7_CONFIG		0xFFC01DC8	/* DMA1 Channel 7 Configuration register */
#define DMA1_7_NEXT_DESC_PTR	0xFFC01DC0	/* DMA1 Channel 7 Next Descripter Ptr Reg */
#define DMA1_7_START_ADDR	0xFFC01DC4	/* DMA1 Channel 7 Start Address */
#define DMA1_7_X_COUNT		0xFFC01DD0	/* DMA1 Channel 7 Inner Loop Count */
#define DMA1_7_Y_COUNT		0xFFC01DD8	/* DMA1 Channel 7 Outer Loop Count */
#define DMA1_7_X_MODIFY		0xFFC01DD4	/* DMA1 Channel 7 Inner Loop Addr Increment */
#define DMA1_7_Y_MODIFY		0xFFC01DDC	/* DMA1 Channel 7 Outer Loop Addr Increment */
#define DMA1_7_CURR_DESC_PTR	0xFFC01DE0	/* DMA1 Channel 7 Current Descriptor Pointer */
#define DMA1_7_CURR_ADDR	0xFFC01DE4	/* DMA1 Channel 7 Current Address Pointer */
#define DMA1_7_CURR_X_COUNT	0xFFC01DF0	/* DMA1 Channel 7 Current Inner Loop Count */
#define DMA1_7_CURR_Y_COUNT	0xFFC01DF8	/* DMA1 Channel 7 Current Outer Loop Count */
#define DMA1_7_IRQ_STATUS	0xFFC01DE8	/* DMA1 Channel 7 Interrupt Status Register */
#define DMA1_7_PERIPHERAL_MAP	0xFFC01DEC	/* DMA1 Channel 7 Peripheral Map Register */