hw.c

QNX ADS BSP code for i.MX27 chips

/*
 * $QNXLicenseC: 
 * Copyright 2007, QNX Software Systems.  
 *  
 * Licensed under the Apache License, Version 2.0 (the "License"). You  
 * may not reproduce, modify or distribute this software except in  
 * compliance with the License. You may obtain a copy of the License  
 * at: http://www.apache.org/licenses/LICENSE-2.0  
 *  
 * Unless required by applicable law or agreed to in writing, software  
 * distributed under the License is distributed on an "AS IS" basis,  
 * WITHOUT WARRANTIES OF ANY KIND, either express or implied. 
 * 
 * This file may contain contributions from others, either as  
 * contributors under the License or as licensors under other terms.   
 * Please review this entire file for other proprietary rights or license  
 * notices, as well as the QNX Development Suite License Guide at  
 * http://licensing.qnx.com/license-guide/ for other information. 
 * $
 */


#include "proto.h"

int mx21_i2c_start(mx21_dev_t *dev, int read)
{
	uint16_t i, cr, address;
	/*
	 * Set the slave address and the requested transfer mode
	 * in the data register
	 */
	address = dev->slave_addr << 1;
	if (read)
		address |= 0x01;
 
	/* Set the Master bit */
	cr = in16(dev->regbase + MX21_I2C_CR) | MX21_I2CR_MSTA;
	out16(dev->regbase + MX21_I2C_CR, cr);



	/* Wait till the Bus Busy bit is set */
	for (i = 0; i < 16; i++) {
		if (in16(dev->regbase + MX21_I2C_SR) & MX21_I2SR_IBB)
		break;
		nanospin_ns(1000);
	}

	if (i == 16)
		return -1;

	/* Set the Transmit bit */
	cr = in16(dev->regbase + MX21_I2C_CR) | MX21_I2CR_MTX;
	out16(dev->regbase + MX21_I2C_CR, cr);

	out16(dev->regbase + MX21_I2C_DR, address);
	return 0;
}

void mx21_i2c_stop(mx21_dev_t *dev)
{
	uint16_t cr;

	cr = in16(dev->regbase + MX21_I2C_CR) & ~(MX21_I2CR_MSTA | MX21_I2CR_MTX);
	out16(dev->regbase + MX21_I2C_CR, cr);
}

void mx21_i2c_enable(mx21_dev_t *dev)
{

  if(dev->stop)
      {
   		/* Clear the status register */
		out16(dev->regbase + MX21_I2C_SR,  0x00);
      }
  else
       	out16(dev->regbase + MX21_I2C_CR,  MX21_I2CR_RSTA); 
	    	
		/* Enable I2C and its interrupts */
		if (dev->options & MX21_OPT_POLLING) {
 			out16(dev->regbase + MX21_I2C_CR,  MX21_I2CR_EN);
		}
		else {
 				out16(dev->regbase + MX21_I2C_CR,  MX21_I2CR_EN);
				out16(dev->regbase + MX21_I2C_CR,  MX21_I2CR_EN | MX21_I2CR_IEN);
		}  	
}

/*
 * Disables the I2C module.
 */
void mx21_i2c_disable(mx21_dev_t *dev)
{
   	out16(dev->regbase + MX21_I2C_CR, 0);
}

int
mx21_wait_complete(mx21_dev_t *dev, int read)
{
	int	i, sr, cr, tx_success = 0;

	if (dev->options & MX21_OPT_POLLING) {
		for (i = 0; i < 0x100; i++) {
			if (in16(dev->regbase + MX21_I2C_SR) & MX21_I2SR_IIF)
				break;
			nanospin_ns(1000);
		}

		if (i == 0x100)
			return -1;

		sr = in16(dev->regbase + MX21_I2C_SR);
		cr = in16(dev->regbase + MX21_I2C_CR);
		out16(dev->regbase + MX21_I2C_SR, 0);

		/* Check if RXAK is received in Transmit mode */
		if ((cr & MX21_I2CR_MTX) && (!(sr & MX21_I2SR_RXAK)))
			tx_success = 1;
	}
	else {
		uint64_t	ntime = 1e9;
		int			intrerr = EOK;

		while (intrerr != ETIMEDOUT) {
			TimerTimeout(CLOCK_MONOTONIC, _NTO_TIMEOUT_INTR, NULL, &ntime, NULL);
			intrerr = InterruptWait_r(0, NULL);
			sr = in16(dev->regbase + MX21_I2C_SR);
			if (sr & MX21_I2SR_IIF) {
				cr = in16(dev->regbase + MX21_I2C_CR);
				out16(dev->regbase + MX21_I2C_SR, 0);	/* Clear status */
				InterruptUnmask(dev->irq, dev->iid);

				/* Check if RXAK is received in Transmit mode */
				if ((cr & MX21_I2CR_MTX) && (!(sr & MX21_I2SR_RXAK)))
					tx_success = 1;

				break;
			}
		}
	}

	if (!read) {
		if (!tx_success)
			return -1;
	}

	return 0;
}